From its companion post The Dawn of the SoC 2.0 Era: The ARM Perspective
Source of the slide: ARM Cortex系列核心介绍 (Core ARM Cortex Series Introduction, 52RD, April 13, 2015)
Regarding TSMC itself the April 8 conclusion in TSMC Outlines 16nm, 10nm Plans article by EE|Times is:
“It’s not completely clear who is ahead at 16/14 but I think TSMC is making a major commitment to trying to be ahead at 10,” Jones said. “If that happens and TSMC has closed the gap with Intel, the issue is then if TSMC’s 10 and Intel’s 10 are the same,” he said.
Background from the April 14, 2015 TSMC Symposium: “10nm is Ready for Design Starts at This Moment” article in Cadence Communities Blog:
The 10nm semiconductor process node is no longer in the distant future – it is here today, according to presenters at the recent TSMC 2015 Technology Symposium in San Jose, California. TSMC executives noted that EDA tools have been certified, most of the IP is ready or close to ready, and risk production is expected to begin in the fourth quarter of 2015.
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Here are some more details about 10nm at TSMC as presented in talks by Dr. Cliff Hou, vice president of R&D at TSMC (right), and Dr. BJ Woo, vice president of business development at TSMC (below left). At the TSMC Symposium, speakers also introduced two new process nodes, 16HHC and 28HPC+ (see blog post here).
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According to Woo, TSMC is not only keeping up with Moore’s Law – it is running ahead of the law with its 10FF offering. “We have done a lot more aggressive scaling than Moore’s Law demands for our 10nm technology,” she said. A case in point is the fully functional 256Mb SRAM with a cell size that is approximately 50% smaller than the 16FF+ cell size. She called this an “exceptional shrink ratio” that goes beyond traditional scaling.
And it’s not just SRAM. The 10FF node, Woo said, can scale key pitches by more than 70%. Combine that with innovative layout, and 10nm can achieve almost 50% die size scaling compared to 16FF+. “And this is very, very aggressive,” she said.
After noting that the 16FF+ already provides “clear performance leadership,” Woo said that 10FF offers a 22% performance gain over 16FF+ at the same power, or more than 40% power reduction at the same speed. This comparison is based on a TSMC internal ring oscillator benchmark circuit. For the Cortex-A57 test chip used to validate EDA tools, the result was a 19% speed increase at the same power, and a 38% power reduction at the same speed.
New features in 10FF include a unidirectional (1D) layout style and new local interconnect layer. These features help 10FF achieve a 2.1X logic density improvement over 16FF+, whereas normally TSMC gets about a 1.9X density boost for node migration, Woo said. In addition to the density improvement, the 1D Mx architecture can reduce CD (critical dimension) variation by 60%, she said.
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And an already remarkable quote from April 12, 2015 TSMC Symposium: New Low-Power Process, Expanded R&D Will Drive Vast Innovation: TSMC Executive article in Cadence Communities Blog:
Hock Tan, CEO of Avago, described a symbiotic relationship between TSMC and his company that led to a super high-density switch for a networking customer, implemented in 16FF+. The switch has 96 ports, each running 100G Gbps, and drawing less than 2W each. That enables, in a next-generation data center, the tripling of a switch performance to more than 10 Tbps.
Moreover, according to the April 12, 2015 TSMC Symposium: New 16FFC and 28HPC+ Processes Target “Mainstream” Designers and Internet of Things (IoT) article from Cadence Communities Blog:
16FFC is a “compact” version of the 16nm FinFET+ (16FF+) process technology that is now in risk production at TSMC. It claims advantages in power, performance, and area compared to the existing 16FF+ process, along with easy migration from 16FF+. It can be used for ultra low-power IoT applications such as wearables, mobile, and consumer.
28HPC+ is an improved version of the 28HPC (High Performance Compact) process, which is itself a fairly recent development. Late last year 28HPC went into volume production, and it provides a 10% smaller die size and 30% power reduction compared to TSMC’s earlier 28LP process. 28HPC+ ups the ante by providing 15% faster speed at the same leakage, or 30-50% reduction in leakage at the same speed, compared to 28HPC.
TSMC also provided updates on other processes on its roadmap, which includes the following:
High Performance – 28HP, 28HPM, 20SoC, 16FF+
Mainstream – 28LP, 28HPC, 28HPC+, 16FFC
Ultra Low Power – 55ULP, 40ULP, 28ULP, 16FFC (16FFC is in both mainstream and low power categories)
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In connection with that remember the September 29, 2014 announcement:
TSMC Launches Ultra-Low Power Technology Platform for IoT and Wearable Device Applications
TSMC (TWSE: 2330, NYSE: TSM) today announced the foundry segment’s first and most comprehensive ultra-low power technology platform aimed at a wide range of applications for the rapidly evolving Internet of Things (IoT) and wearable device markets that require a wide spectrum of technologies to best serve these diverse applications. In this platform, TSMC offers multiple processes to provide significant power reduction benefits for IoT and wearable products and a comprehensive design ecosystem to accelerate time-to-market for customers.
TSMC’s ultra-low power process lineup expands from the existing 0.18-micron extremely low leakage (0.18eLL) and 90-nanometer ultra low leakage (90uLL) nodes, and 16-nanometer FinFET technology, to new offerings of 55-nanometer ultra-low power (55ULP), 40ULP and 28ULP, which support processing speeds of up to 1.2GHz. The wide spectrum of ultra-low power processes from 0.18-micron to 16-nanometer FinFET is ideally suited for a variety of smart and power-efficient applications in the IoT and wearable device markets. Radio frequency and embedded Flash memory capabilities are also available in 0.18um to 40nm ultra-low power technologies, enabling system level integration for smaller form factors as well as facilitating wireless connections among IoT products.
Compared with their previous low power generations, TSMC’s ultra-low power processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption and enable significant increases in battery life — by 2X to 10X — when much smaller batteries are demanded in IoT/wearable applications.
“This is the first time in the industry that we offer a comprehensive platform to meet the demands and innovation for the versatile Internet of Things market where ultra-low power and ubiquitous connectivity are most critical,” said TSMC President and Co-CEO, Dr. Mark Liu. “Bringing such a wide spectrum of offerings to this emerging market demonstrates TSMC’s technology leadership and commitment to bring great value to our customers and enable design wins with competitive products.”
One valuable advantage offered by TSMC’s ultra-low power technology platform is that customers can leverage TSMC’s existing IP ecosystem through the Open Innovation Platform®. Designers can easily re-use IPs and libraries built on TSMC’s low-power processes for new ultra-low power designs to boost first-silicon success rates and to achieve fast time-to-market product introduction. Some early design engagements with customers using 55ULP, 40ULP and 28ULP nodes are scheduled in 2014 and risk productions are planned in 2015.
“TSMC’s new ultra-low power process technology not only reduces power for always-on devices, but enables the integration of radios and FLASH delivering a significant performance and efficiency gain for next-generation intelligent products,” said Dr. Dipesh Patel, executive vice president and general manager, physical design group, ARM. “Through a collaborative partnership that leverages the energy-efficient ARM® Cortex®-M and Cortex-A CPUs and TSMC’s new process technology platform, we can collectively deliver the ingredients for innovation that will drive the next wave of IoT, wearable, and other connected technologies.”
“Low power is the number one priority for Internet-of-Things and battery-operated mobile devices,” said Martin Lund, Senior Vice President and General Manager of the IP Group at Cadence. “TSMC’s new ULP technology platform coupled with Cadence’s low-power mixed-signal design flow and extensive IP portfolio will better meet the unique always-on, low-power requirements of IoT and other power sensitive devices worldwide.”
“CSR has an unequalled reputation in Bluetooth technology and has been instrumental in its progression, including helping to write the Bluetooth Smart standard that is meeting the demands of today’s rapidly evolving consumer electronics market,” said Joep van Beurden, CEO at CSR. “For many years, CSR has closely collaborated with TSMC, and we are pleased to demonstrate the results of that collaboration with the adoption of the 40ULP platform for our next generation of Bluetooth Smart devices including products for markets like smart home, lighting and wearables that are enabling the growth of the Internet of Things. Our solutions simplify complex customer challenges and help speed their time to market by allowing them to design and deliver breakthrough low power wireless connected products on these powerful new platforms.”
“The imaging SoC solutions of Fujitsu Semiconductor Limited bring the best balance between high imaging quality and low power consumption, to meet the significant demand from our customers and the electronics market,” said Tom Miyake, Corporate Vice President, at System LSI Company of Fujitsu Semiconductor Limited. “We welcome that TSMC is adding the 28ULP technology to its successful 28nm platform. We believe this technology will provide our SoCs with the key feature: low power consumption at low cost.”
“Nordic Semiconductor has been a pioneer and leader in ultra-low power wireless solutions since 2002, and with the launch of its nRF51 Series of Systems-on-Chip (SoCs) in 2012 the company established itself as a leading vendor of Bluetooth Smart wireless technology,” said Svenn-Tore Larsen, CEO of Nordic Semiconductor. “We have been collaborating closely with TSMC on the selection of process technology for our upcoming nRF52 Series of ultra-low power RF SoCs. I am happy to announce that we have selected the TSMC 55ULP platform. This process is a key enabler for us to push the envelope on power consumption, performance and level of integration of the nRF52 Series to meet the future requirements of Wearable and Internet of Things applications.”
“Built on TSMC’s Ultra-Low Power technology platform and comprehensive design ecosystem, Realtek’s Bluetooth Energy Efficient smart SoC, BEE, supports the latest Bluetooth 4.1 specification featuring Bluetooth Low Energy (BLE) and GATT-based profiles,” said Realtek Vice President and Spokesman, Yee-Wei Huang. “BEE’s power efficient architecture, low power RF, and embedded Flash are ideal both for the IoT and for wearable devices such as smart watches, sport wristbands, smart home automation, remote controls, beacon devices, and wireless charging devices.”
“Silicon Labs welcomes TSMC’s ultra-low power initiative because it will enable a range of energy-friendly processing, sensing and connectivity technologies we are actively developing for the Internet of Things,” said Tyson Tuttle, Chief Executive Officer, Silicon Labs. “We look forward to continuing our successful collaboration with TSMC to bring our solutions to market.”
“Synopsys is fully aligned with TSMC on providing designers with a broad portfolio of high-quality IP for TSMC’s ultra-low power process technology and the Internet of Things applications,” said John Koeter, Vice President of Marketing for IP and Prototyping at Synopsys. “Our wide range of silicon-proven DesignWare® interface, embedded memory, logic library, processor, analog and subsystem IP solutions are already optimized to help designers meet the power, energy and area requirements of wearable device SoCs, enabling them to quickly deliver products to the market.”
As well as the ARM and Cadence Expand Collaboration for IoT and Wearable Device Applications Targeting TSMC’s Ultra-Low Power Technology Platform announcement of Sept 29, 2015:
ARM® and Cadence® today announced an expanded collaboration for IoT and wearable devices targeting TSMC’s ultra-low power technology platform. The collaboration will enable the rapid development of IoT and wearable devices by optimizing the system integration of ARM IP and Cadence’s integrated flow for mixed-signal design and verification, and their leading low-power design and verification flow.
The partnership will deliver reference designs and physical design knowledge to integrate ARM Cortex® processors, ARM CoreLink™ system IP, and ARM Artisan® physical IP along with RF/analog/mixed-signal IP and embedded flash in the Virtuoso®-VDI Mixed-Signal Open Access integrated flow for the new TSMC process technology offerings of 55ULP, 40ULP and 28ULP.
“TSMC’s new ULP technology platform is an important development in addressing the IoT’s low-power requirements,” stated Nimish Modi, senior vice president of Marketing and Business Development at Cadence. “Cadence’s low-power expertise and leadership in mixed-signal design and verification form the most complete solution for implementing IoT applications. These flows, optimized for ARM’s Cortex-M processors including the new Cortex-M7, will enable designers to develop and deliver new and creative IoT applications that take maximum advantage of ULP technologies.”
“The reduction in leakage of TSMC’s new ULP technology platform combined with the proven power-efficiency of Cortex-M processors will enable a vast range of devices to operate in ultra energy-constrained environments,” said Richard York, vice president of embedded segment marketing, ARM. “Our collaboration with Cadence enables designers to continue developing the most innovative IoT devices in the market.”
This new collaboration builds on existing multi-year programs to optimize performance, power and area (PPA) via Cadence’s digital, mixed-signal and verification flows and complementary IP alongside ARM Cortex-A processors and ARM POP™ IP targeting TSMC 40nm, 28nm, and 16nm FinFET process technologies. Similarly, the companies have been optimizing the solution based around the Cortex-M processors in mixed-signal SoCs targeting TSMC 65/55nm and larger geometry nodes. The joint Cortex-M7 Reference Methodology for TSMC 40LP is the latest example of this collaboration.
For the above keep in mind The TSMC Grand Alliance [TSMC, Dec 3, 2013]:
The TSMC Grand Alliance is one of the most powerful force for innovation in the semiconductor industry, bringing together our customers, EDA partners, IP partners, and key equipment and materials suppliers at a new, higher level of collaboration.
The objectives of the TSMC Grand Alliance are straightforward: to help our customers, the alliance members and ourselves win business and stay competitive.
We know collaboration works. We have seen it in the great strides our customers and ecosystem members have made through the Open Innovation Platform® where today there are 5,000 qualified IP macros and over 100 EDA tools that supports our customers’ innovation and helps them attain maximum value from TSMC’s technology.
Today Open Innovation Platform is an unmatchable design ecosystem and a key part of the Grand Alliance that will prove much more powerful. Looking at R&D investment alone, we calculate that TSMC and ten of our customers invest more in R&D than the top two semiconductor IDMs combined.
Through the Grand Alliance TSMC will relentlessly pursue our mission and collaborate with customers and partners. We need each other to be competitive. We need each other to win. Such is the power of the Grand Alliance.
[Some more information is in the very end of this post]
A related overview in Kicking off #ARMWearablesWK with an analysts view of the market post of November 17, 2014 of ARM Connected Community blog by David Blaza:
Today as we kickoff ARM Wearables Week we hear from Shane Walker of IHS who is their Wearables and Medical market expert.
Shane’s take on this market is that it’s for real this time (there was a brief Smartwatch wave a few years ago) and will continue to be a hot growth sector through 2015. One of the great benefits of talking with analysts like Shane is they help you think through what’s going on and bust a few myths that may have found their way into our thinking. For example I asked Shane what the barriers to growth were and he carefully and patiently pointed out that Wearables are growing at a 21% CAGR already and will hit $12b in device sales this year (without services, more on that later in the week). So this is not an emerging or promising market, it’s here and growing at an impressive rate. By 2019 Shane’s estimate is that it will hit $33.5b in device sales and services are increasingly going to factor into the wearables experience (Big Data is coming!).
Shane breaks the Wearables market down to 5 major categories:
Healthcare and Medical
Fitness and Wellness
Infotainment
Industrial
Military
I’m glad he did this for me because wearables are incredibly diverse and this week you are going to see some category defying products here such as smart Jewelry where does that fit?
Below you can see a
table
chart that Shane was willing to share that shows his estimate for market size and units sold, the main learning for me is how much of this market is healthcare related. Also attached below are details on what services IHS offer in the Wearables market or you can find them here.
attached is: Wearable Technology Intelligence Service 2014.pdf [IHS Technology, November 17, 2014]
Note the following table in that:
More information:
– A Guide to the $32b Wearables Market [IHS Technology, March 11, 2015]
– which has a free to download whitepaper:
Wearable Technology: The Small Revolutions is Making Big Waves
Brief retrospective on the SoC 1.0 Era
Detailed Background from TSMC’s quaterly calls
Q1 2015:
Mark Liu – TSMC – President & Co-CEO
[update on new technology]
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The continuous demand of more functionality and integration in smartphones drives for more silicon content. We expect smartphones will continue to drive our growth in the next several years.
In the meantime, we see IoT appears us — present us new growth opportunities. The proliferation of IoT not only will bring us growth in the sensor, connectivity and advanced packaging areas, the associated application and services, such as big data analytics, will also further our growth in the computation space, including application processor, network processor, image processor, graphic processor, microcontroller and other various processors. That was the long-term outlook.
I’ll update some of our 10-nanometer development progress. Our 10-nanometer technology development is progressing well. Our technology qualification remains in Q4 this year.
Recently we have successfully achieved fully functional yields of our 256-megabit SRAM. Currently we have more than 10 customers fully engaged with us on 10-nanometer. We still expect to have 10-nanometer volume ramp in fourth quarter 2016 and to contribute billing in early 2017.
This technology adopts our third-generation FinFET transistor and have scaling more than one generation. Its price is fully justified by its value for various applications, including application processor, baseband SoC, network processor, CPU and graphic processors. Its cost and price ratio will comply to our structural profitability considerations.
As for new technology development at TSMC, I’d like to start with — to update you our 7-nanometer development. We have started our 7-nanometer technology development program early last year. We also have rolled out our 7-nanometer design and technology collaboration activity with several of our major customers. Our 7-nanometer technology developments today are well in progress.
TSMC’s 7-nanometer technology will leverage most of the tools used in 10-nanometer, in the meantime achieve a new generation of technology value to our customers. The 7-nanometer technology risk production date is targeted at early 2017.
Now I would like to give you an update on EUV. We have been making steady progress on EUV. Both our development tools, we have two NXE 3300 have been upgraded to the configuration of 80 watt of EUV power, with an average wafer throughput of a few hundred wafers per day. We continue to work with ASML to improve tool stability and availability. We also are working with ASML and our partners on developing the infrastructure of EUV, such as masks and resists.
Although today the process on record of both 10-nanometers and 7-nanometer are on immersion tools, with innovative multiple patterning techniques, we will continue to look for opportunity to further reduce the wafer cost and simplify the process flow by inserting EUV layer in the process.
Now I’d like to give you an update of our recently announced ultra-low-power technologies. We have offered the industry’s most comprehensive ultra-low-power technology portfolio, ranging from 55-nanometer ULP, 40-nanometer ULP, 28-nanometer ULP, to the recently announced 16 FFC, a compact version of 16 FinFET Plus, enable continual reduction of operating voltage and power consumption. Today more than 30 product tape-outs planned in 2015 from more than 25 customers.
This 55- and 40-nanometer ULP will be the most cost-effective solution for low- to mid-performance wearable and IoT devices. The 28 ULP and 16 FFC will be the most power-efficient solution for high-performance IoT applications. In particular, our 16 FFC offers the ultra-low-power operation at a supply voltage of 0.55 volts, with higher performance than all of the FD-SOI technologies marketed today.
Lastly I’ll give you an update of our recent IoT specialty technology development. We have developed the world’s first 1.0-micron pixel size 16-megapixel CMOS image sensor, with stacked image signal processor, which was announced in March by our customer for the next-generation smartphone. Secondly, we continue to drive the best low resistance in BCD [Bipolar-CMOS-DMOS for DC-to-DC converter: together with Ultra-High-Voltage (UHV) technology for AC-to-DC converter—are the key to enable monolithic integrated PMIC design] technology roadmap, from 0.18 micron to 0.13 micron and from 8-inch to 12-inch production for wireless charging and fast wired charging of mobile devices. We continue to extend our 0.13 BCD technology from consumer and industrial applications to automotive-grade electrical system control applications.
Lastly, recently we have started production in foundry’s first 40-nanometer industrial embedded Flash technology that was started from November last year. And this technology recently passed automotive-grade qualification, that was in March, for engine control applications.
C.C. Wei – TSMC – President & Co-CEO
I will update you the 28-nanometer, 20 and 16 FinFET status and also our InFO business.
First, 28-nanometer. This is the fifth year since TSMC’s 28-nanometer entered mass production. 28-nanometer has been a very large and successful node for us. Our market segment share at this node has held up well and is in the mid-70s this year. We expect this to continue in year 2016. In comparison, this is better than what we had in the 40-nanometer node.
The demand for 28-nanometer is expected to grow this year due to the growth of mid- and low-end smartphones and as well as the second-wave segment, such as radio frequency, circuit product and the Flash controllers that migrate into this node.
However, due to some customers’ inventory adjustments, which we believe is only going to be for the short term, the demand for 28-nanometer in the second quarter will be lower than our previous quarter, resulting in 28-nanometer capacity utilization rate to be in the high-80s range. But we expect the utilization rate of the 28-nanometer to recover soon and to be above 90% in the second half of this year.
While we are in the mass production, we also continue to improve the performance of our technology. Last year we have introduced our 28-HPC, which is a compact version of 28-HPM. For the purpose of helping 64-bit CPU conversion for mid- to low-end market, this year we further improved the 28-HPC to 28-HPC Plus. For comparison, 28-HPC Plus will have 18% power consumption — lower power consumption at the same speed or 15% faster speed at the same kind of power.
As for the competitive position, we are confident that we will continue to lead in performance and yield. So far we do not see there is a very much effective capacity in High K metal gate at 28-nanometer outside TSMC. And since we have already shipped more than 3m 12-inch 28-nanometer wafers, the learning curve has given us an absolute advantage in cost.
Now let me move to our 20 SoC. TSMC remains the sole solution provider in foundry industry for 20-nanometer process. Our yield has been consistently good after a very successful ramp last year. But recently we have observed customers’ planned schedule for product migration from 20 nanometer to 16 FinFET started sooner than we forecasted three months ago.
As a result, even we continue to grow 20-nanometer business in the second quarter of this year, our earlier forecast of 20-nanometer contributing above 20% of total wafer revenue this year has to be revised down by a few points to a level about the mid teens. That being the case, we still forecast the revenue from 20-nanometer will more than double that of year 2014’s level.
Now 16 FinFET. The schedule for 16 FinFET high-volume production remains unchanged. We will begin ramping in the third quarter this year. And the ramp rate appeared be faster than we forecasted three months ago, thanks to the excellent yield learning that we can leverage our 20-nanometer experience and also due to a faster migration from 20-nanometer to 16 FinFET.
In addition to good yield, our 16 FinFET device performance also met all products’ specs due to our very good transistor engineering. So we believe our 16 FinFET will be a very long-life node due to its good performance and the right cost. This is very similar to our 28-nanometer node.
We are highly confident that our 16 FinFET is very competitive. As we’ve said repeatedly, combining 20-nanometer and 16-nanometer, we will have the largest foundry share in year 2015. And if we only look at 16-nanometer alone, we still can say TSMC will have the largest 16- or 14-nanometer foundry share in year 2016.
Now let me move to our InFO business update. The schedule to ramp up the InFO in second quarter next year remains unchanged. We expect InFO will contribute more than $100m quarterly revenue by next year, fourth quarter next year, when it will be fully ramped.
Right now we are building a new facility in Longtan, that’s a city very near to Hsinchu, where our headquarters are, for ramping up InFO. Today a small product line is almost complete and it’s ready for early engineering experiment. This pilot line will be expanded to accommodate the high-volume ramp in year 2016.
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Andrew Lu – Barclays – Analyst
… I think Mark presented at the Technology Symposium in San Jose mentioned that 16 FinFET versus competing technology is about 10% performance better. So can you elaborate what’s 10% performance better? If our die size is larger than our competitors, how can we get the 10% performance better?
Mark Liu – TSMC – President & Co-CEO
In the conference we talked about 16 FinFET Plus. That is our second-generation FinFET transistor. In that we improved our transistor performance a great deal. According to our information, that transistor speed, talk about speed at fixed power, is higher than the competitor by 10%. That’s what I meant. … Because of the transistor structure, transistor engineering.
Andrew Lu – Barclays – Analyst
Compared to competing — is the competing the current competitor’s solution or the next-generation competitor’s solution? For example, LPE versus LPP or something like that?
Mark Liu – TSMC – President & Co-CEO
The fastest one. The fastest.
Andrew Lu – Barclays – Analyst
Their best one?
Mark Liu – TSMC – President & Co-CEO
Yes.
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Dan Heyler – BofA Merrill Lynch – Analyst
My second question is relating to 20-nanometer. Here you certainly have a lot of growth in 16, with customers taping out aggressively, especially next year. Given your high share at 28, how do you keep 28 full? You obviously have a lot of technology there. Customers will move forward.
So I’m wondering, could you elaborate on new areas that are actually creating new demand at 28, such that you can continue to grow 28 next year. And do you think you can grow? I think previously you said maybe hold it at current levels even with 16 growing. So just maybe revisit that question.
C.C. Wei – TSMC – President & Co-CEO
To answer the question, I think the high-end smartphone will move to 16 FinFET. However, the mid- to — and lower-end smartphones will stay in the 28-nanometer because that’s very cost effective. And mid- and low-end smartphone continues to grow significantly. So that will give a very strong demand on 28-nanometer. In addition, we still have a second-wave product, like RF and Flash controller, as I use as an example, move into 28-nanometer.
So summing it up, I think the 28-nanometer’s demand continue to grow while we move into the 16 FinFET for high-end smartphone.
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Michael Chou – Deutsche Bank – Analyst
As Mark has highlighted your EUV program, Does that imply you may consider using EUV in the second stage of your 16-nanometer — 10-nanometer ramp-up, potentially in 2018 or 2019?
Mark Liu – TSMC – President & Co-CEO
Yes, we always look for opportunity to insert EUV in both 10-nanometer and 7-nanometer. The EUV technology provides not only some cost benefit, but also simplify the process. That means you can replace multiple layers with one layer that helps your yield improvement. So there’s opportunity both in quality and cost always exist so long as EUV’s productivity comes to the threshold point.
And in — as you noticed on 10-nanometer, our capacity build will largely done in 2016 and 2017. So 2018 will be inserted, if inserted, will be combined with some other tools upgrade, some tool upgrade to 7, for example, and replaced by the EUV tools. In that node it will not be a fresh capacity build with EUV at that time because that’s a little bit late in the schedule for the 10.
7-nanometer, of course it will be higher probability adopting EUV. And the benefit will be bigger because the 7-nanometer has a lot of multiple layers, quadruple, even multiple patterning layers, thus EUV can be more effective in reducing the cost and improve the yield, for example. So that’s our current status.
But today EUV is still in the engineering mode. The productivity, as you heard, will still have some gaps for practical insertion of the technology. So we’re still working on that, in that mode. And we have — although we have one-day performance up to 1,000 wafer per day, but I was talking about average still a few hundreds. And we need to get to more than 1,000 to consider a schedule to put it into the production.
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Randy Abrams – Credit Suisse – Analyst
… As you go to fourth quarter, how broad is the customer base? Is it a single key product or are you seeing broadening out of 16 FinFET as you ramp that in fourth quarter?
Mark Liu – TSMC – President & Co-CEO
… As for the second half, we think, first of all, the inventory adjustment will largely complete towards the end of second quarter.
We think the end market of smartphone is still healthy growth this year. Therefore the second half will resume the growth. And, more importantly, our 16 FinFET technology will start to ramp in the second half. So that will contribute a lot of growth, more than the 20-nanometer shipment reduction. So those two factors.
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Roland Shu – Citigroup – Analyst
My first question is on given the fast ramp of 16-nanometer, so are we going to see meaningful revenue contribution for 16 in 3Q?
C.C. Wei – TSMC – President & Co-CEO
We ramp up in third quarter this year, but it’s many layers of process, plus about one month is back-end. So in 3Q we expect just the revenue just very minimum.
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Bill Lu – Morgan Stanley – Analyst
This is a follow-up to Randy’s question. But I’m going to go over some numbers with you first before I ask the question, which is we did the math. I don’t think these are exactly right. But over the last five years we’ve got IDM zero growth, fabless 8%, but system houses above 20%, right. So system houses, I’m excluding memory, just the system LSI, the logic portion. I think that might be slightly conservative.
Now that’s a pretty big change. And I’m wondering how you should think about that, how you should — if you look at TSMC addressing the system houses versus the fabless customers, if you look at, for example, your market share, if you look at your margin for the system houses versus the fabless, how do you think about that?
Mark Liu – TSMC – President & Co-CEO
Yes. Indeed, in the past five years the system houses sourcing and foundry business to us has a much higher growth rate, as you quoted. But remember, that came from a very small base. Okay? But we welcome system house sourcing because we consider them are fabless too, fabless companies, the companies without fabs, bring business to us.
It’s not necessarily the margin has to do with what type of company sourced. It has to do with our value to that company and also the size, the size of the business. If the business is bigger, of course the — we probably can enjoy a slightly — a little bit better price. So it depends on the size of the business, less dependent on what company, system company or non-system company’s business.
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Steven Pelayo – HSBC – Analyst
For the last three years or so, TSMC’s been growing 20%, 30% year-on-year revenue growth rates. First quarter 50% year on year. But to Bill’s question there, it does look like in the second half of the year, if I play around with your full-year guidance and what you’re doing, low single-digit year-on-year growth rates. And if we exclude maybe 16-nanometer, above 16-nanometer, maybe it’s flat to down. Is that the new industry? What are we talking now for industry growth rates for both the semi industry and in the foundry market this year?
90 days ago you suggested the semi market was going to grow 5% this year with foundries growing 12%. In light of your new guidance, in light of what it looks like you’re going to have very slight year-on-year growth rates in the second half of the year, what do you think that means for the overall industry?
Mark Liu – TSMC – President & Co-CEO
We think the semiconductor growth this year currently is indeed we adjusted down from 5% earlier to 4% at this time. Yes. We think it’s really due to the macroeconomic situation around the world today. And therefore the foundry market — foundry growth rate will adjusted down too. We are looking at about 10% range. So that’s why we revised our view on the current semiconductor growth.
Brett Simpson – Arete Research – Analyst
My question on 10-nanometer, I know it’s still 18 months away from ramp-up, but can you talk about how fast this ramp might scale relative to 20-nanometer or 28-nanometer?
And as you ramp up 10-nanometer for high-end smartphones, would you expect low-end smartphones to start migration from 28 with 16 FinFET in 2017?
Elizabeth Sun – TSMC – Director of Corporate Communications
… Your question seems to say that if we ramp 10-nanometer in the future, which will be targeting the high-end smartphone, will the low-end smartphone be migrating from 28-nanometer into 16-nanometers.
Brett Simpson – Arete Research – Analyst
And just to add to that, Elizabeth, how quickly will 10-nanometer scale up relative to the scaling of 20-nanometer — the ramp-up of 20-nanometer and 28? Will it be as fast?
Elizabeth Sun – TSMC – Director of Corporate Communications
So the profile of the 10-nanometer ramp, will that be steeper than the profile of the 20 or the 28-nanometer?
Mark Liu – TSMC – President & Co-CEO
Okay. The first part of the question has to do with 10-nanometer ramp for the high-end smartphone, will the mid/low-end move to 16? I think we — this is up to our customers’ product portfolio. We definitely know a lot of customer is looking at 28-nanometer to use — to do as the low end. But the specification, the smartphone processor specification changes constantly. So what portion of that product will move to 16-nanometer? We think definitely there are some portion, but how a big portion really depends on their product strategy.
On the 10-nanometer ramp, I wouldn’t say it’s bigger. But at least it’s similar scale of our ramp as we do in 16 and as we do in 20.
Brett Simpson – Arete Research – Analyst Great.
Thank you. And let me just have a follow-up here. There’s been a lot of talk in the industry about one of your larger customers [Qualcomm] planning to introduce a new application processor on both Samsung’s 14-nanometer process as well as your 16 FinFET for the same chip later this year. And we haven’t really seen a single chip get taped out on two new processors at the same time before in the industry. So my question, how does this really work between the two foundries? Does it mean that that one customer can adjust dynamically, month to month, how they allocate wafers between you and Samsung? Or am I — or how might this work?
Elizabeth Sun – TSMC – Director of Corporate Communications … So your question seems to say that there is a customer that appeared to be working with two different foundries on the 14 and 16-nanometer node. And the products are about to arrive. You would like to understand how this customer will be allocating month by month the — what’s the production or the orders with both of the two foundries. Is that your question?
Brett Simpson – Arete Research – Analyst
Yes, that’s right. Whether they can move around dynamically how they allocate wafers. That’s right.
C.C. Wei – TSMC – President & Co-CEO
Well my answer is very typical. Our 16 FinFET is really very competitive. And we did not know that customer going to — how they’re going to allocate. I cannot even make any comment on that.
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Gokul Hariharan – JPMorgan – Analyst
First of all on 16-nanometer, since Dr. Wei mentioned that next year a lot of demand on entry-level to mid-end smartphone is still going to stay at 28-nanometer, could you talk about your visibility for second-wave demand for 16-nanometer?
What is the visibility that you have? Is it going to be really strong? Because you mentioned that a lot of the cost-sensitive customers would still stay on 28, at least for next year.
C.C. Wei – TSMC – President & Co-CEO
For 28-nanometer I said mid to low end this year that, and next year probably, that smartphone will stay in 28-nanometer because it’s very cost-effective and performance-wise is very good. For 16 FinFET I think that people will start to move with their product plan and some of the mid-end smartphone will move into 16-nanometer. That’s for sure.
In addition to that, we also see improving our 16 FinFET ultra-lower-power Mark just mentioned. And that will have a lot of application. And every product, lower power consumption is one of that advantage.
And so that would be our second wave of 16 FinFET.
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Dan Heyler – BofA Merrill Lynch – Analyst
… So on 16, this FinFET Compact which is getting introduced, when would we expect to see that in volume production?
C.C. Wei – TSMC – President & Co-CEO
FFC? That will be ready next year. And we expect that high-volume production starts probably two years later. That’s year 2017. 2018 will reach the high volume.
Dan Heyler – BofA Merrill Lynch – Analyst
Okay. So is there a — so the cost-down version for mid-end phones FinFET that you alluded to, plus low power, when is that available?
C.C. Wei – TSMC – President & Co-CEO
Probably in 2017 second half.
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Q4’2014:
Lora Ho – Taiwan Semiconductor Manufacturing Company Ltd – SVP and CFO
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During the fourth quarter, the strong 20-nanometer ramp was mainly driven by communication-related applications. As a result, communication grew 18% sequentially and the revenue contribution increased from 59% in the third quarter to 65% in the fourth quarter. As for other applications, computer grew 7%, while consumer and industrial declined 21% and 11% respectively.
On a full-year basis, communication increased 39% and represented 59% of our revenue. The major contributing segments included baseband, application processors, image processors and display drivers. Another fast-growing application in 2014 was industrial and standard, which grew 30% year over year. The growth was mainly driven by increasing usage of power management ICs, near-field communications and audio codec within the mobile devices.
By technology, 20-nanometer revenue contribution started with a very small number in the second quarter, jumped to 9% in the third quarter and reached 21% in the fourth quarter. Such unprecedented ramp cannot be achieved without seamless teamwork with our customer, the R&D and operational people in TSMC.
On a full-year basis, 20 nanometer accounted for about 9% of our full-year wafer revenue. Looking forward, we are confident that 20 nanometer will continue its momentum to contribute 20% of the revenue for the whole year 2015.
Meanwhile, customer demand for our 28-nanometer wafers remained strong. Accordingly, these two advanced technologies, 20 nanometer plus 28 nanometer, represented 51% of our fourth-quarter total wafer revenue, a big increase from 43% in the third quarter.
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Mark Liu – Taiwan Semiconductor Manufacturing Company Ltd – President and Co-CEO
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Now I’ll give you a few words on 10-nanometer development update. Our 10-nanometer technology development is progressing and our qualification schedule at the end of 2015, end of this year, remains the same. We are now working with customers for their product tape-outs. We expect its volume production in 2017.
On the new technology development in TSMC, I’ll begin with beyond 10 nanometer I just talked about. We are now working on our future-generation platform technology development, with separate dedicated R&D development teams. These technologies will be offered in the 2017-to-2019 period. We are committed to push forward our technology envelope along the silicon scaling path.
In addition to the silicon device scaling, we are also working on the system scaling through advanced packaging to increase system bandwidth, to decrease power consumption and device form factors. Our first-generation InFO technology has been qualified. Currently we are qualifying customer InFO products with 16-nanometer technology. And it will be ready for volume ramp next year, 2016. We are now working on our second-generation InFO technology to supplement the silicon scaling of 10-nanometer generation.
On the other side, in addition to the recently announced 55ULP ultra-low power technology, 40ULP, 28ULP technologies for ultra-low power application, such as wearable and IoT, we are also working on 16ULP technology development. This 16ULP design kit will be available in June this year. It will be just suitable for both high-performance and ultra-low power or ultra-low voltage, less than 0.6-volt applications.
C.C. Wei – Taiwan Semiconductor Manufacturing Company Ltd – President and Co-CEO<