I use Mojo-IDE to programme a FPGA Spartan 6. My problem is when I compile the project the IDE display the following error messages:
Failed to parse Verilog value: CLK_PER_BIT
Failed to parse Verilog value: CLK_RATE
The problem occur since I updated the libraries.
NOTE: This is a part of the text that print when compiling:
Thanks and sorry for me english.