When trying to build the Processor Subsytem attached I get a critical warning related to the TSU input clock.
CRITICAL WARNING: [BD 17-148] Frequency mismatch between port /ps_SUBSYS/zynq_ultra_ps_e_0/EMIO_ENET_TSU_CLK : 144 and user selected paraameter PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ : 143.75 of IP /ps_SUBSYS/zynq_ultra_ps_e_0
I would like to make sure that this is not a real issue and that using a clock of 143.75 for the TSU is valid.