Hi,
In my design i've got an external memory which can be read and write by the PS or by the PCIe link. Each of this master is connected to an AXI interconnect which connected to others IP and the memory controller.
But i've got some issues when the PCIe and the PS want to access the memory. I want to give priority to PS, and i saw that there is arbitration options in the AXI Interconnect. But i don't really understood how it works.
Is the interconnect stops the AXI access from PCIe (which has less priority) in order to perform the AXI access from PS (which i want to have a high priority) ? For example, my memory is a 32-bit width, and through the PCIe i want to read 128bits. So, if i well understand, the AXI interconnect will "split" the AXI PCIe acces in 4 memory accesses. But in this case, what is the behavior of the AXI Interconnect if the PS makes an AXI access during the PCie access ?
Thank you for your help to understand the arbitration behavior on the AXI Interconnect.
Regards