Hi all,
I am trying to develop a verilog design, in which I want to use 6 GTH transceivers from the left side and 6 GTH transceivers from the right side. I am starting a new project and I add from IP catalog (menu FPGA features and Desgin -> IO interfaces) one IP core (GTH left side) and I open the example design in order to generate the output products. Now, in this step I add -following the previous way- a second IP core for generating the right side's GTH transceivers. When the second IP core is generated (I tried both choices global and out of context per IP) the verilog files are in read-only mode. I used the tcl command set_property IS_MANAGED false [get_files <name>.xci] in order to make the second IP editable. After using this tcl command the read-only mode in not active and I can modify the verilog files. I have added the module in the top design and for example I added an extra input pin in the GTH module that inserts a new clock. Now, when I try to synthesize my design, I get an error that the port connection I added does not exist in the verilog file. It seems that, when I try to modify the verilog files of the second IP the changes are not allowed even in the case that I used the previous tcl command that turns the IP status to user-managed IP.
How can I edit according to my needs the second IP? Which is the solution for this problem?
Looking forward to your feedback.
baskat13