This if how I did that in my cartridges and it works fine.
vbat.png
I was looking at this and I see your low pass filter (56pF cap, 1k resistor), and diode (low passing 1 edge, not the other).
I had added the M2+100nS delay circuit because I remember needing that delay when I wrote VHDL code for MMC1 a long time ago. But I don’t remember why now. Do you know if these 2 things are both accomplishing the same purpose? I will also look into this but I am just having trouble remembering what that was all about now.
D+R+C adds about 50ns delay on falling edge of WRAM /CE because M2 and /ROMSEL does not change at the same time. If you have this delay in FPGA, you can omit that (but I think it is still good to have this circuit on board, if you dont want to use it, just solder tin blob as jumper in place of resistor and do not solder other elements.
Statistics: Posted by krzysiobal — Sun Apr 21, 2024 10:26 pm