Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:
* High Performance Computing
* Industrial / Scientific / Medical (ISM)
Xilinx is looking for a talented, self-driven and motivated software engineer to be part of the Xilinx System Level Simulation Methodology and Tools team. The individual will focus on System Level Simulation and Verification flows and related automation within the tool framework. The framework is applicable to all Xilinx Design tools, namely Vivado and the various SDx Software Defined development environment. Vivado Tool Suite is Xilinx’s primary IDE that enables users to do System Level Design. It is a revolutionary design environment built to accelerate the design and verification of our 'All Programmable' FPGAs, SoCs and 3D ICs. The SDx family of software defined development environment includes the SDAccel, the SDSoC and the SDNet tools.
As a member of this high-performance team, the selected candidate will be responsible for extending the Xilinx Vivado and Xilinx’s new SDx development environments to enable system level simulation and emulation infrastructure, debug and profile of the design. The candidate has opportunity to work on developing a new tool environment from an early stage and leave his/her personal mark on the tool. The selected candidate will take ownership of simulation related infrastructure and flows. He / She will ensure that these features meet technical specifications and business goals, and assume responsibility for improving the quality of the solution. The candidate will be involved in all aspects of product development; design, prototyping, testing, and productization.
The team provides a fast-paced start-up like environment offering each of its members immense opportunity to interact with a wide variety of people including from other organizations like marketing, sales, support, and even direct customer interaction, and truly learn and grow their skills and capabilities.
* A minimum of Bachelors in EE, CS, CE with 6 years of relevant work experience
* Strong background in simulation, verification and debug methodologies and corresponding software tool infrastructure.
* Experience in creating large scale models using SystemC TLM 2.0 is required.
* Experience in atleast one of the technologies like Virtual Platforms, SystemC/QEMU models, Emulation platforms, Hw/Sw co-design, and Performance analysis is required.
* Familiarity with hardware languages like VHDL, Verilog and System Verilog for simulation using tools like Modelsim, VCS, Questa Sim is rquired.
* Strong software development and debug skills, fluency in C/C++ including OOP, data structures, and algorithms is required. Experience in software development environment on Linux and/or Windows.
* Any exposure to compiler technologies, especially LLVM, is a big plus.
* Background in Electronic Design Automation (EDA) tool flows is required including general awareness of ASIC or FPGA design creation / verification flows including synthesis, place and route. Familiarity with IP based design creation flows including IP-XACT is advantageous.
* Be able to excel in a team environment.
* Demonstrated ability to identify technical problems, propose viable options, and apply technical solutions.
* Excellent verbal and written communication skills including experience across organizational boundaries and multiple geographies.