Samsung Electronics, world’s largest semiconductor manufacturer (according to SIA) just won the race to 10 nanometer (10nm-class) process by launching DDR4 SDRAM memory chips which utilize the new process node. However, this ’10nm-class’ is not exactly precise 10nm, as the distance between the cells / transistors can vary between 10-19nm. If you’re in the semiconductor industry, this will not be surprising as Intel’s famous 22nm process was considered 26-28nm process.
The new DDR4 memory chips come in 8Gbit (1GB) capacity, supporting the frequency of up to 3.2 GHz (1.6 GHz in DDR mode). At the same time, power consumption is reduced by 10% when compared to the last-gen 20nm DDR4 chips. As a reference, 20nm DDR4 DRAM came in 4Gbit (512KB) capacity and worked up to 2.4 GHz (1.2 GHz DDR). Given that now Samsung Electronics can fit approximately 30% more chips onto the same 300mm wafer, the company expects to drop the price of new memory in double digit figures.
“Samsung’s 10nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry,” said Young-Hyun Jun, President of Memory Business, Samsung Electronics. “In the near future, we will also launch next-generation, 10nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users.”
The very first 10nm DDR4 comes to market as 16GB SODIMM and DIMM modules.
While the initial memory modules carry 16GB capacity, we should see the arrival of 32 and 64GB in standard form factor, and 128-256GB memory modules in double-height factor, enabling memory capacity to skyrocket. When the first SODIMM and DIMM memory hits the market, we should see high-performance mobile and desktop systems coming with 32, 64 and 128GB, while the servers could easily max out the 1.5 TB supported by Xeon E5 v4 (Broadwell-EP) processors.
You can read the rest of press release here:
Samsung Electronics, the world leader in advanced memory technology, announced today that it has begun mass producing the industry’s first 10-nanometer (nm) class* , 8-gigabit (Gb) DDR4 (double-data-rate-4) DRAM chips and the modules derived from them. DDR4 is quickly becoming the most widely produced memory for personal computers and IT networks in the world, and Samsung’s latest advancement will help to accelerate the industry-wide shift to advanced DDR4 products.
Samsung opened the door to “10nm-class DRAM” for the first time in the industry after overcoming technical challenges in DRAM scaling. These challenges were mastered using currently available ArF (argon fluoride) immersion lithography, free from the use of EUV (extreme ultra violet) equipment.
Samsung’s roll-out of the 10nm-class (1x) DRAM marks yet another milestone for the company after it first mass produced 20-nanometer (nm)** 4Gb DDR3 DRAM in 2014.
Samsung’s leading-edge 10nm-class 8Gb DDR4 DRAM significantly improves the wafer productivity of 20nm 8Gb DDR4 DRAM by more than 30 percent.
The new DRAM supports a data transfer rate of 3,200 megabits per second (Mbps), which is more than 30 percent faster than the 2,400Mbps rate of 20nm DDR4 DRAM. Also, new modules produced from the 10nm-class DRAM chips consume 10 to 20 percent less power, compared to their 20nm-process-based equivalents, which will improve the design efficiency of next-generation, high-performance computing (HPC) systems and other large enterprise networks, as well as being used for the PC and mainstream server markets.
The industry-first 10nm-class DRAM is the result of Samsung’s advanced memory design and manufacturing technology integration. To achieve an extremely high level of DRAM scalability, Samsung has taken its technological innovation one step further than what was used for 20nm DRAM. Key technology developments include improvements in proprietary cell design technology, QPT (quadruple patterning technology***) lithography, and ultra-thin dielectric layer**** deposition.
Unlike NAND flash memory, in which a single cell consists of only a transistor, each DRAM cell requires a capacitor and a transistor that are linked together, usually with the capacitor being placed on top of the area where the transistor rests. In the case of the new 10nm-class DRAM, another level of difficulty is added because they have to stack very narrow cylinder-shaped capacitors that store large electric charges, on top of a few dozen nanometer-wide transistors, creating more than eight billion cells.
Samsung successfully created the new 10nm-class cell structure by utilizing a proprietary circuit design technology and quadruple patterning lithography. Through quadruple patterning, which enables use of existing photolithography equipment, Samsung also built the core technological foundation for the development of the next-generation 10nm-class DRAM (1y).
In addition, the use of a refined dielectric layer deposition technology enabled further performance improvements in the new 10nm-class DRAM. Samsung engineers applied ultra-thin dielectric layers with unprecedented uniformity to a thickness of a mere single-digit angstrom (one 10 billionth of a meter) on cell capacitors, resulting in sufficient capacitance for higher cell performance.
Based on its advancements with the new 10nm-class DDR4 DRAM, Samsung expects to also introduce a 10nm-class mobile DRAM solution with high density and speed later this year, which will further solidify its leadership in the ultra-HD smartphone market.
While introducing a wide array of 10nm-class DDR4 modules with capacities ranging from 4GB for notebook PCs to 128GB for enterprise servers, Samsung will be extending its 20nm DRAM line-up with its new 10nm-class DRAM portfolio throughout the year.
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