Integrated Circuit Design Hardware Software Project Leadership Experienced senior integrated circuit designer with a proven track record for successful execution on all areas of a chip. Excellent communicator, skilled in bringing together team members to resolve fullchip issues. Summary of Qualifications Over 12 years of Mixedsignal circuit design including SRAM memory, Decoder, and IO interface design Project management experience on a EEPROM chip product and on a software development project Worked with product engineers to perform postsilicon board level functional test and debug Mentored several engineers technically and as a manager. Directly managed an 18person technical team. ASIC VLSI Design and Programming experience with CC, Perl, and Assembly Language Algorithm profiling Experience with Cadence Virtuoso, Synopsys Design and IC Compiler, HSPICE IEEE Senior Member PROFESSIONAL EXPERIENCE Project Manager, VariQ Contractor to U.S. DHS, Washington, DC Jul 2014 Present Program and Technical Project Manager for a multimillion dollar Software Development contract with the U.S. Department of Homeland Security. Leading a team consisting of 38 individuals with 4 subcontractors. Led the efforts in scope and resource management, scheduling, and staff training, as well as involved in hiring decisions. Directly interface with government clients and senior management team to ensure project execution is in line with schedule, scope, and budget. Sr Systems Engineer, ISI University of Southern California, Arlington, VA Jan 2013 Jun 2014 Research engineer in the VLSI design of a powerefficient FPGA utilizing 3D integrated circuit design with a DRAM memory stack Architecture exploration and Domainspecific hardIP RTL digital design and synthesis. Involved in business development efforts in emerging memory technologies and 3DIC design. Evaluation of novel SplitFabrication manufacturing approach for IP protection and design obfuscation Transistorlevel Testcircuit design for functional and reliability assessment using the latest Process Design Kits PDK Semiconductor Design Engineering Supervisor, Micron Technology, Folsom, CA Apr 2008 Dec 2010 One of the technical lead on the development of the first memory chip product utilizing a novel, disruptive technology PhaseChange Memory at the 90nm process node. Played a key role in the technical product development of a Flashmemory chip utilizing a disruptive technology, Phase Change Memory. This required working with teams from different locations Italy, Shanghai, Philippines, as well as crossfunctional teams Marketing, Processdevelopment, and Customer Architecture teams. Applied statistical methods for device characterization and modeling for resistive memories, including aging and drift simulations. Senior Design Manager, Flash Memory WCCG Group, Intel Corp., Folsom, CA Jun 2000 Mar 2008 Worked through the product life cycle of 8 circuit design projects, which required supervising Design, Layout, and Product Engineers on the development of embedded and ASIC memory chips. Integration of a novel Phase Change Memory PCM electrical device into a Flash memory circuit Architecture definition, array layout feasibility studies, fullchip power performance, logic circuits Responsible for design of array decoding circuits, optimized for read speed program current Owned assemblylanguage microcode to control programming sequence on first PCM product Conducted experiments to characterize PCM array and provide a statistical model of the behavior Developed an inhouse memory compiler tool suite C Perl and led a crossdivisional 8member working group to proliferate the internal memory compiler to various divisions. EDUCATION Certifications PMP, CSM, CMMI for Development 2012, MBA in Strategy Finance, GPA 3.56, GMAT 730800 Indian School of Business ISB, India 2000, M.S. in Electrical Engineering, VLSI Circuit Design Area, CGPA 3.334.0 Virginia Tech, Blacksburg, VA Thesis Development of a LowPower SRAM Memory Compiler, ISCAS, May 2001 1998, B. S. in Electrical Engineering Computer Engineering double major Virginia Tech, Blacksburg, VA Minor in Computer Science and Mathematics Jefferson Labs Continuous Electron Beam Accelerator Facility Intern, Newport News, VA NASA Langley Electrical Engineering Mentorship Student, Hampton, VA PUBLICATIONS Y. Leow, A. Dasu, M. Jagasivamani, A. Akoglu, Methodology for Architecture Exploration of a Power Efficient 3D FPGA Stack, IEEE DAC, June 2014. M. Jagasivamani, P. Gadfort, M. Sika, M. Bajura, M. Fritze, Split Fabrication Obfuscation Metrics and Techniques, IEEE HOST, May 2014. M. Bajura, M. Sika, M. Jagasivamani, J. Ahlbin, I. Sanchez, S. Stansberry, M. Fritze, Z. Sparling, V. Tyree, N. Cockerham, R. Pina, R. Wormuth, W. Hansford, Enabling SplitFabrication for the IARPA Trusted Integrated Chips TIC Program, Proc. of the 2014 GOMACTech, March 2014. J. Granacki, B. Calhoun, A. Dasu, M. Jagasivamani, L. Mcllrath, M. Fritze, LEDRA A 3DIC UltraLow Power FPGA Architecture for DoD Applications, Proc. of the 2014 GOMACTech, March 2014. M. Jagasivamani, M. Bajura, M. Fritze, Dual Threshold Voltage Adder for Robust SubVt Operation in 65nm Technology, IEEE S3S Microelectronics conference, Oct 2013. F. Bedeschi, R. Fackenthal, C. Resta, E. Donze, M. Jagasivamani, et al., A BipolarSelected PhaseChange Memory Featuring MultiLevel Cell Storage, IEEE J. of SolidState, vol. 44, no. 1, pp. 217227, Jan. 2009. F. Bedeschi, R. Fackenthal, C. Resta, E. Donze, M. Jagasivamani, et al., A MultiLevelCell BipolarSelected PhaseChange Memory, Proceedings of ISSCC, pp. 428625, Feb 2008. F. Bedeschi, R. Fackenthal, C. Resta, E. Donze, M. Jagasivamani, et al., A MultiLevelCell BipolarSelected PhaseChange Memory, IEDM Special Session, Dec 2008. 9. M. Jagasivamani and D.S. Ha, Development of a LowPower SRAM Compiler, IEEE International Conference on Circuits and Systems, Volume 4, pp. 498501, May 2001. PATENTS Patent 8064265 M. Jagasivamani, et al, Programming BitAlterable Memories. Patent 7848133 R. Fackenthal, M. Jagasivamani, Phase Change Memory with Bipolar Junction Transistor Select Device. Patent 8018763 R. Fackenthal, F. Bedeschi, M. Jagasivamani, et al., Adaptive Wordline Programming Bias of a Phase Change Memory. Patent 7869269 E. Donze, F. Bedeschi, M. Jagasivamani, PhaseChange Memory Device with Error Correction Capability. Patent 7940553 P. Wu, R. Fackenthal, F. Bedeschi, M. Jagasivamani, et al., Method of Storing an Indication of whether a Memory Location in Phase Change Memory needs Programming. ACHIEVEMENTS 1. Successfully filed 5 US Patents on circuit design innovations. 2. Published and Presented at Industry technical conferences IEEE HOST, ISSCC, ISCAS, DAC 3. Part of the Design group that won industrylevel EDN magazines Innovator of the Year award for 2009, given to a single electronics engineering team across the entire industry for innovation in product design and technical leadership. PERSONAL DHS Public Trust Clearance, Citizenship Status US Citizen