This table will be used in a follow-on patch to allow specifying
Power7 events by name rather than by their raw codes.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
tools/perf/arch/powerpc/util/power7-events.h | 3315 ++++++++++++++++++++++++++
1 file changed, 3315 insertions(+)
create mode 100644 tools/perf/arch/powerpc/util/power7-events.h
diff --git a/tools/perf/arch/powerpc/util/power7-events.h b/tools/perf/arch/powerpc/util/power7-events.h
new file mode 100644
index 0000000..a2f928b
--- /dev/null
+++ b/tools/perf/arch/powerpc/util/power7-events.h
@@ -0,0 +1,3315 @@
+#ifndef __POWER7_EVENTS_H__
+#define __POWER7_EVENTS_H__
+
+/*
+* File: power7_events.h
+* CVS:
+* Author: Corey Ashford
+* cjashfor@us.ibm.com
+* Mods: Sukadev Bhattiprolu
+* sukadev@linux.vnet.ibm.com
+* Mods: <your name here>
+* <your email address>
+*
+* (C) Copyright IBM Corporation, 2009. All Rights Reserved.
+* Contributed by Corey Ashford <cjashfor.ibm.com>
+*
+* Note: This code was generated based on power7-events.h in libpfm4
+*
+* Documentation on the PMU events can be found at:
+* http://www.power.org/documentation/comprehensive-pmu-event-reference-power7
+*/
+
+static const struct perf_pmu_event power7_pmu_events[] = {
+{
+ .name = "PM_IC_DEMAND_L2_BR_ALL",
+ .code = 0x4898,
+ .short_desc = " L2 I cache demand request due to BHT or redirect",
+ .long_desc = " L2 I cache demand request due to BHT or redirect",
+},
+{
+ .name = "PM_GCT_UTIL_7_TO_10_SLOTS",
+ .code = 0x20a0,
+ .short_desc = "GCT Utilization 7-10 entries",
+ .long_desc = "GCT Utilization 7-10 entries",
+},
+{
+ .name = "PM_PMC2_SAVED",
+ .code = 0x10022,
+ .short_desc = "PMC2 Rewind Value saved",
+ .long_desc = "PMC2 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.",
+},
+{
+ .name = "PM_CMPLU_STALL_DFU",
+ .code = 0x2003c,
+ .short_desc = "Completion stall caused by Decimal Floating Point Unit",
+ .long_desc = "Completion stall caused by Decimal Floating Point Unit",
+},
+{
+ .name = "PM_VSU0_16FLOP",
+ .code = 0xa0a4,
+ .short_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt) ",
+ .long_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt) ",
+},
+{
+ .name = "PM_MRK_LSU_DERAT_MISS",
+ .code = 0x3d05a,
+ .short_desc = "Marked DERAT Miss",
+ .long_desc = "Marked DERAT Miss",
+},
+{
+ .name = "PM_MRK_ST_CMPL",
+ .code = 0x10034,
+ .short_desc = "marked store finished (was complete)",
+ .long_desc = "A sampled store has completed (data home)",
+},
+{
+ .name = "PM_NEST_PAIR3_ADD",
+ .code = 0x40881,
+ .short_desc = " Nest events (MC0/MC1/PB/GX), Pair3 ADD",
+ .long_desc = " Nest events (MC0/MC1/PB/GX), Pair3 ADD",
+},
+{
+ .name = "PM_L2_ST_DISP",
+ .code = 0x46180,
+ .short_desc = "All successful store dispatches",
+ .long_desc = "All successful store dispatches",
+},
+{
+ .name = "PM_L2_CASTOUT_MOD",
+ .code = 0x16180,
+ .short_desc = "L2 Castouts - Modified (M, Mu, Me)",
+ .long_desc = "An L2 line in the Modified state was castout. Total for all slices.",
+},
+{
+ .name = "PM_ISEG",
+ .code = 0x20a4,
+ .short_desc = "ISEG Exception",
+ .long_desc = "ISEG Exception",
+},
+{
+ .name = "PM_MRK_INST_TIMEO",
+ .code = 0x40034,
+ .short_desc = "marked Instruction finish timeout ",
+ .long_desc = "The number of instructions finished since the last progress indicator from a marked instruction exceeded the threshold. The marked instruction was flushed.",
+},
+{
+ .name = "PM_L2_RCST_DISP_FAIL_ADDR",
+ .code = 0x36282,
+ .short_desc = " L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+ .long_desc = " L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
+},
+{
+ .name = "PM_LSU1_DC_PREF_STREAM_CONFIRM",
+ .code = 0xd0b6,
+ .short_desc = "LS1 'Dcache prefetch stream confirmed",
+ .long_desc = "LS1 'Dcache prefetch stream confirmed",
+},
+{
+ .name = "PM_IERAT_WR_64K",
+ .code = 0x40be,
+ .short_desc = "large page 64k ",
+ .long_desc = "large page 64k ",
+},
+{
+ .name = "PM_MRK_DTLB_MISS_16M",
+ .code = 0x4d05e,
+ .short_desc = "Marked Data TLB misses for 16M page",
+ .long_desc = "Data TLB references to 16M pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+ .name = "PM_IERAT_MISS",
+ .code = 0x100f6,
+ .short_desc = "IERAT Miss (Not implemented as DI on POWER6)",
+ .long_desc = "A translation request missed the Instruction Effective to Real Address Translation (ERAT) table",
+},
+{
+ .name = "PM_MRK_PTEG_FROM_LMEM",
+ .code = 0x4d052,
+ .short_desc = "Marked PTEG loaded from local memory",
+ .long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to the same module this proccessor is located on due to a marked load or store.",
+},
+{
+ .name = "PM_FLOP",
+ .code = 0x100f4,
+ .short_desc = "Floating Point Operation Finished",
+ .long_desc = "A floating point operation has completed",
+},
+{
+ .name = "PM_THRD_PRIO_4_5_CYC",
+ .code = 0x40b4,
+ .short_desc = " Cycles thread running at priority level 4 or 5",
+ .long_desc = " Cycles thread running at priority level 4 or 5",
+},
+{
+ .name = "PM_BR_PRED_TA",
+ .code = 0x40aa,
+ .short_desc = "Branch predict - target address",
+ .long_desc = "The target address of a branch instruction was predicted.",
+},
+{
+ .name = "PM_CMPLU_STALL_FXU",
+ .code = 0x20014,
+ .short_desc = "Completion stall caused by FXU instruction",
+ .long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.",
+},
+{
+ .name = "PM_EXT_INT",
+ .code = 0x200f8,
+ .short_desc = "external interrupt",
+ .long_desc = "An interrupt due to an external exception occurred",
+},
+{
+ .name = "PM_VSU_FSQRT_FDIV",
+ .code = 0xa888,
+ .short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!",
+ .long_desc = "DP vector versions of fdiv,fsqrt ",
+},
+{
+ .name = "PM_MRK_LD_MISS_EXPOSED_CYC",
+ .code = 0x1003e,
+ .short_desc = "Marked Load exposed Miss ",
+ .long_desc = "Marked Load exposed Miss ",
+},
+{
+ .name = "PM_LSU1_LDF",
+ .code = 0xc086,
+ .short_desc = "LS1 Scalar Loads ",
+ .long_desc = "A floating point load was executed by LSU1",
+},
+{
+ .name = "PM_IC_WRITE_ALL",
+ .code = 0x488c,
+ .short_desc = "Icache sectors written, prefetch + demand",
+ .long_desc = "Icache sectors written, prefetch + demand",
+},
+{
+ .name = "PM_LSU0_SRQ_STFWD",
+ .code = 0xc0a0,
+ .short_desc = "LS0 SRQ forwarded data to a load",
+ .long_desc = "Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.",
+},
+{
+ .name = "PM_PTEG_FROM_RL2L3_MOD",
+ .code = 0x1c052,
+ .short_desc = "PTEG loaded from remote L2 or L3 modified",
+ .long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a remote module due to a demand load or store.",
+},
+{
+ .name = "PM_MRK_DATA_FROM_L31_SHR",
+ .code = 0x1d04e,
+ .short_desc = "Marked data loaded from another L3 on same chip shared",
+ .long_desc = "Marked data loaded from another L3 on same chip shared",
+},
+{
+ .name = "PM_DATA_FROM_L21_MOD",
+ .code = 0x3c046,
+ .short_desc = "Data loaded from another L2 on same chip modified",
+ .long_desc = "Data loaded from another L2 on same chip modified",
+},
+{
+ .name = "PM_VSU1_SCAL_DOUBLE_ISSUED",
+ .code = 0xb08a,
+ .short_desc = "Double Precision scalar instruction issued on Pipe1",
+ .long_desc = "Double Precision scalar instruction issued on Pipe1",
+},
+{
+ .name = "PM_VSU0_8FLOP",
+ .code = 0xa0a0,
+ .short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ",
+ .long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) ",
+},
+{
+ .name = "PM_POWER_EVENT1",
+ .code = 0x1006e,
+ .short_desc = "Power Management Event 1",
+ .long_desc = "Power Management Event 1",
+},
+{
+ .name = "PM_DISP_CLB_HELD_BAL",
+ .code = 0x2092,
+ .short_desc = "Dispatch/CLB Hold: Balance",
+ .long_desc = "Dispatch/CLB Hold: Balance",
+},
+{
+ .name = "PM_VSU1_2FLOP",
+ .code = 0xa09a,
+ .short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+ .long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+},
+{
+ .name = "PM_LWSYNC_HELD",
+ .code = 0x209a,
+ .short_desc = "LWSYNC held at dispatch",
+ .long_desc = "Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.",
+},
+{
+ .name = "PM_PTEG_FROM_DL2L3_SHR",
+ .code = 0x3c054,
+ .short_desc = "PTEG loaded from remote L2 or L3 shared",
+ .long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.",
+},
+{
+ .name = "PM_INST_FROM_L21_MOD",
+ .code = 0x34046,
+ .short_desc = "Instruction fetched from another L2 on same chip modified",
+ .long_desc = "Instruction fetched from another L2 on same chip modified",
+},
+{
+ .name = "PM_IERAT_XLATE_WR_16MPLUS",
+ .code = 0x40bc,
+ .short_desc = "large page 16M+",
+ .long_desc = "large page 16M+",
+},
+{
+ .name = "PM_IC_REQ_ALL",
+ .code = 0x4888,
+ .short_desc = "Icache requests, prefetch + demand",
+ .long_desc = "Icache requests, prefetch + demand",
+},
+{
+ .name = "PM_DSLB_MISS",
+ .code = 0xd090,
+ .short_desc = "Data SLB Miss - Total of all segment sizes",
+ .long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.",
+},
+{
+ .name = "PM_L3_MISS",
+ .code = 0x1f082,
+ .short_desc = "L3 Misses ",
+ .long_desc = "L3 Misses ",
+},
+{
+ .name = "PM_LSU0_L1_PREF",
+ .code = 0xd0b8,
+ .short_desc = " LS0 L1 cache data prefetches",
+ .long_desc = " LS0 L1 cache data prefetches",
+},
+{
+ .name = "PM_VSU_SCALAR_SINGLE_ISSUED",
+ .code = 0xb884,
+ .short_desc = "Single Precision scalar instruction issued on Pipe0",
+ .long_desc = "Single Precision scalar instruction issued on Pipe0",
+},
+{
+ .name = "PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE",
+ .code = 0xd0be,
+ .short_desc = "LS1 Dcache Strided prefetch stream confirmed",
+ .long_desc = "LS1 Dcache Strided prefetch stream confirmed",
+},
+{
+ .name = "PM_L2_INST",
+ .code = 0x36080,
+ .short_desc = "Instruction Load Count",
+ .long_desc = "Instruction Load Count",
+},
+{
+ .name = "PM_VSU0_FRSP",
+ .code = 0xa0b4,
+ .short_desc = "Round to single precision instruction executed",
+ .long_desc = "Round to single precision instruction executed",
+},
+{
+ .name = "PM_FLUSH_DISP",
+ .code = 0x2082,
+ .short_desc = "Dispatch flush",
+ .long_desc = "Dispatch flush",
+},
+{
+ .name = "PM_PTEG_FROM_L2MISS",
+ .code = 0x4c058,
+ .short_desc = "PTEG loaded from L2 miss",
+ .long_desc = "A Page Table Entry was loaded into the TLB but not from the local L2.",
+},
+{
+ .name = "PM_VSU1_DQ_ISSUED",
+ .code = 0xb09a,
+ .short_desc = "128BIT Decimal Issued on Pipe1",
+ .long_desc = "128BIT Decimal Issued on Pipe1",
+},
+{
+ .name = "PM_CMPLU_STALL_LSU",
+ .code = 0x20012,
+ .short_desc = "Completion stall caused by LSU instruction",
+ .long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.",
+},
+{
+ .name = "PM_MRK_DATA_FROM_DMEM",
+ .code = 0x1d04a,
+ .short_desc = "Marked data loaded from distant memory",
+ .long_desc = "The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load.",
+},
+{
+ .name = "PM_LSU_FLUSH_ULD",
+ .code = 0xc8b0,
+ .short_desc = "Flush: Unaligned Load",
+ .long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.",
+},
+{
+ .name = "PM_PTEG_FROM_LMEM",
+ .code = 0x4c052,
+ .short_desc = "PTEG loaded from local memory",
+ .long_desc = "A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.",
+},
+{
+ .name = "PM_MRK_DERAT_MISS_16M",
+ .code = 0x3d05c,
+ .short_desc = "Marked DERAT misses for 16M page",
+ .long_desc = "A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.",
+},
+{
+ .name = "PM_THRD_ALL_RUN_CYC",
+ .code = 0x2000c,
+ .short_desc = "All Threads in run_cycles",
+ .long_desc = "Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work.",
+},
+{
+ .name = "PM_MEM0_PREFETCH_DISP",
+ .code = 0x20083,
+ .short_desc = " Nest events (MC0/MC1/PB/GX), Pair1 Bit1",
+ .long_desc = " Nest events (MC0/MC1/PB/GX), Pair1 Bit1",
+},
+{
+ .name = "PM_MRK_STALL_CMPLU_CYC_COUNT",
+ .code = 0x3003f,
+ .short_desc = "Marked Group Completion Stall cycles (use edge detect to count #)",
+ .long_desc = "Marked Group Completion Stall cycles (use edge detect to count #)",
+},
+{
+ .name = "PM_DATA_FROM_DL2L3_MOD",
+ .code = 0x3c04c,
+ .short_desc = "Data loaded from distant L2 or L3 modified",
+ .long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load",
+},
+{
+ .name = "PM_VSU_FRSP",
+ .code = 0xa8b4,
+ .short_desc = "Round to single precision instruction executed",
+ .long_desc = "Round to single precision instruction executed",
+},
+{
+ .name = "PM_MRK_DATA_FROM_L21_MOD",
+ .code = 0x3d046,
+ .short_desc = "Marked data loaded from another L2 on same chip modified",
+ .long_desc = "Marked data loaded from another L2 on same chip modified",
+},
+{
+ .name = "PM_PMC1_OVERFLOW",
+ .code = 0x20010,
+ .short_desc = "Overflow from counter 1",
+ .long_desc = "Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+},
+{
+ .name = "PM_VSU0_SINGLE",
+ .code = 0xa0a8,
+ .short_desc = "FPU single precision",
+ .long_desc = "VSU0 executed single precision instruction",
+},
+{
+ .name = "PM_MRK_PTEG_FROM_L3MISS",
+ .code = 0x2d058,
+ .short_desc = "Marked PTEG loaded from L3 miss",
+ .long_desc = "A Page Table Entry was loaded into the ERAT from beyond the L3 due to a marked load or store",
+},
+{
+ .name = "PM_MRK_PTEG_FROM_L31_SHR",
+ .code = 0x2d056,
+ .short_desc = "Marked PTEG loaded from another L3 on same chip shared",
+ .long_desc = "Marked PTEG loaded from another L3 on same chip shared",
+},
+{
+ .name = "PM_VSU0_VECTOR_SP_ISSUED",
+ .code = 0xb090,
+ .short_desc = "Single Precision vector instruction issued (executed)",
+ .long_desc = "Single Precision vector instruction issued (executed)",
+},
+{
+ .name = "PM_VSU1_FEST",
+ .code = 0xa0ba,
+ .short_desc = "Estimate instruction executed",
+ .long_desc = "Estimate instruction executed",
+},
+{
+ .name = "PM_MRK_INST_DISP",
+ .code = 0x20030,
+ .short_desc = "marked instruction dispatch",
+ .long_desc = "A marked instruction was dispatched",
+},
+{
+ .name = "PM_VSU0_COMPLEX_ISSUED",
+ .code = 0xb096,
+ .short_desc = "Complex VMX instruction issued",
+ .long_desc = "Complex VMX instruction issued",
+},
+{
+ .name = "PM_LSU1_FLUSH_UST",
+ .code = 0xc0b6,
+ .short_desc = "LS1 Flush: Unaligned Store",
+ .long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)",
+},
+{
+ .name = "PM_INST_CMPL",
+ .code = 0x2,
+ .short_desc = "# PPC Instructions Finished",
+ .long_desc = "Number of PowerPC Instructions that completed.",
+},
+{
+ .name = "PM_FXU_IDLE",
+ .code = 0x1000e,
+ .short_desc = "fxu0 idle and fxu1 idle",
+ .long_desc = "FXU0 and FXU1 are both idle.",
+},
+{
+ .name = "PM_LSU0_FLUSH_ULD",
+ .code = 0xc0b0,
+ .short_desc = "LS0 Flush: Unaligned Load",
+ .long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)",
+},
+{
+ .name = "PM_MRK_DATA_FROM_DL2L3_MOD",
+ .code = 0x3d04c,
+ .short_desc = "Marked data loaded from distant L2 or L3 modified",
+ .long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a marked load.",
+},
+{
+ .name = "PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC",
+ .code = 0x3001c,
+ .short_desc = "ALL threads lsu empty (lmq and srq empty)",
+ .long_desc = "ALL threads lsu empty (lmq and srq empty)",
+},
+{
+ .name = "PM_LSU1_REJECT_LMQ_FULL",
+ .code = 0xc0a6,
+ .short_desc = "LS1 Reject: LMQ Full (LHR)",
+ .long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.",
+},
+{
+ .name = "PM_INST_PTEG_FROM_L21_MOD",
+ .code = 0x3e056,
+ .short_desc = "Instruction PTEG loaded from another L2 on same chip modified",
+ .long_desc = "Instruction PTEG loaded from another L2 on same chip modified",
+},
+{
+ .name = "PM_INST_FROM_RL2L3_MOD",
+ .code = 0x14042,
+ .short_desc = "Instruction fetched from remote L2 or L3 modified",
+ .long_desc = "An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions",
+},
+{
+ .name = "PM_SHL_CREATED",
+ .code = 0x5082,
+ .short_desc = "SHL table entry Created",
+ .long_desc = "SHL table entry Created",
+},
+{
+ .name = "PM_L2_ST_HIT",
+ .code = 0x46182,
+ .short_desc = "All successful store dispatches that were L2Hits",
+ .long_desc = "A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Total for all slices.",
+},
+{
+ .name = "PM_DATA_FROM_DMEM",
+ .code = 0x1c04a,
+ .short_desc = "Data loaded from distant memory",
+ .long_desc = "The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load",
+},
+{
+ .name = "PM_L3_LD_MISS",
+ .code = 0x2f082,
+ .short_desc = "L3 demand LD Miss",
+ .long_desc = "L3 demand LD Miss",
+},
+{
+ .name = "PM_FXU1_BUSY_FXU0_IDLE",
+ .code = 0x4000e,
+ .short_desc = "fxu0 idle and fxu1 busy. ",
+ .long_desc = "FXU0 was idle while FXU1 was busy",
+},
+{
+ .name = "PM_DISP_CLB_HELD_RES",
+ .code = 0x2094,
+ .short_desc = "Dispatch/CLB Hold: Resource",
+ .long_desc = "Dispatch/CLB Hold: Resource",
+},
+{
+ .name = "PM_L2_SN_SX_I_DONE",
+ .code = 0x36382,
+ .short_desc = "SNP dispatched and went from Sx or Tx to Ix",
+ .long_desc = "SNP dispatched and went from Sx or Tx to Ix",
+},
+{
+ .name = "PM_GRP_CMPL",
+ .code = 0x30004,
+ .short_desc = "group completed",
+ .long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.",
+},
+{
+ .name = "PM_STCX_CMPL",
+ .code = 0xc098,
+ .short_desc = "STCX executed",
+ .long_desc = "Conditional stores with reservation completed",
+},
+{
+ .name = "PM_VSU0_2FLOP",
+ .code = 0xa098,
+ .short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+ .long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+},
+{
+ .name = "PM_L3_PREF_MISS",
+ .code = 0x3f082,
+ .short_desc = "L3 Prefetch Directory Miss",
+ .long_desc = "L3 Prefetch Directory Miss",
+},
+{
+ .name = "PM_LSU_SRQ_SYNC_CYC",
+ .code = 0xd096,
+ .short_desc = "A sync is in the SRQ",
+ .long_desc = "Cycles that a sync instruction is active in the Store Request Queue.",
+},
+{
+ .name = "PM_LSU_REJECT_ERAT_MISS",
+ .code = 0x20064,
+ .short_desc = "LSU Reject due to ERAT (up to 2 per cycles)",
+ .long_desc = "Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.",
+},
+{
+ .name = "PM_L1_ICACHE_MISS",
+ .code = 0x200fc,
+ .short_desc = "Demand iCache Miss",
+ .long_desc = "An instruction fetch request missed the L1 cache.",
+},
+{
+ .name = "PM_LSU1_FLUSH_SRQ",
+ .code = 0xc0be,
+ .short_desc = "LS1 Flush: SRQ",
+ .long_desc = "Load Hit Store flush. A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. ",
+},
+{
+ .name = "PM_LD_REF_L1_LSU0",
+ .code = 0xc080,
+ .short_desc = "LS0 L1 D cache load references counted at finish",
+ .long_desc = "Load references to Level 1 Data Cache, by unit 0.",
+},
+{
+ .name = "PM_VSU0_FEST",
+ .code = 0xa0b8,
+ .short_desc = "Estimate instruction executed",
+ .long_desc = "Estimate instruction executed",
+},
+{
+ .name = "PM_VSU_VECTOR_SINGLE_ISSUED",
+ .code = 0xb890,
+ .short_desc = "Single Precision vector instruction issued (executed)",
+ .long_desc = "Single Precision vector instruction issued (executed)",
+},
+{
+ .name = "PM_FREQ_UP",
+ .code = 0x4000c,
+ .short_desc = "Power Management: Above Threshold A",
+ .long_desc = "Processor frequency was sped up due to power management",
+},
+{
+ .name = "PM_DATA_FROM_LMEM",
+ .code = 0x3c04a,
+ .short_desc = "Data loaded from local memory",
+ .long_desc = "The processor's Data Cache was reloaded from memory attached to the same module this proccessor is located on.",
+},
+{
+ .name = "PM_LSU1_LDX",
+ .code = 0xc08a,
+ .short_desc = "LS1 Vector Loads",
+ .long_desc = "LS1 Vector Loads",
+},
+{
+ .name = "PM_PMC3_OVERFLOW",
+ .code = 0x40010,
+ .short_desc = "Overflow from counter 3",
+ .long_desc = "Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+},
+{
+ .name = "PM_MRK_BR_MPRED",
+ .code = 0x30036,
+ .short_desc = "Marked Branch Mispredicted",
+ .long_desc = "A marked branch was mispredicted",
+},
+{
+ .name = "PM_SHL_MATCH",
+ .code = 0x5086,
+ .short_desc = "SHL Table Match",
+ .long_desc = "SHL Table Match",
+},
+{
+ .name = "PM_MRK_BR_TAKEN",
+ .code = 0x10036,
+ .short_desc = "Marked Branch Taken",
+ .long_desc = "A marked branch was taken",
+},
+{
+ .name = "PM_CMPLU_STALL_BRU",
+ .code = 0x4004e,
+ .short_desc = "Completion stall due to BRU",
+ .long_desc = "Completion stall due to BRU",
+},
+{
+ .name = "PM_ISLB_MISS",
+ .code = 0xd092,
+ .short_desc = "Instruction SLB Miss - Tota of all segment sizes",
+ .long_desc = "A SLB miss for an instruction fetch as occurred",
+},
+{
+ .name = "PM_CYC",
+ .code = 0x1e,
+ .short_desc = "Cycles",
+ .long_desc = "Processor Cycles",
+},
+{
+ .name = "PM_DISP_HELD_THERMAL",
+ .code = 0x30006,
+ .short_desc = "Dispatch Held due to Thermal",
+ .long_desc = "Dispatch Held due to Thermal",
+},
+{
+ .name = "PM_INST_PTEG_FROM_RL2L3_SHR",
+ .code = 0x2e054,
+ .short_desc = "Instruction PTEG loaded from remote L2 or L3 shared",
+ .long_desc = "Instruction PTEG loaded from remote L2 or L3 shared",
+},
+{
+ .name = "PM_LSU1_SRQ_STFWD",
+ .code = 0xc0a2,
+ .short_desc = "LS1 SRQ forwarded data to a load",
+ .long_desc = "Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.",
+},
+{
+ .name = "PM_GCT_NOSLOT_BR_MPRED",
+ .code = 0x4001a,
+ .short_desc = "GCT empty by branch mispredict",
+ .long_desc = "Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.",
+},
+{
+ .name = "PM_1PLUS_PPC_CMPL",
+ .code = 0x100f2,
+ .short_desc = "1 or more ppc insts finished",
+ .long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.",
+},
+{
+ .name = "PM_PTEG_FROM_DMEM",
+ .code = 0x2c052,
+ .short_desc = "PTEG loaded from distant memory",
+ .long_desc = "A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store.",
+},
+{
+ .name = "PM_VSU_2FLOP",
+ .code = 0xa898,
+ .short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+ .long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
+},
+{
+ .name = "PM_GCT_FULL_CYC",
+ .code = 0x4086,
+ .short_desc = "Cycles No room in EAT",
+ .long_desc = "The Global Completion Table is completely full.",
+},
+{
+ .name = "PM_MRK_DATA_FROM_L3_CYC",
+ .code = 0x40020,
+ .short_desc = "Marked ld latency Data source 0001 (L3)",
+ .long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+},
+{
+ .name = "PM_LSU_SRQ_S0_ALLOC",
+ .code = 0xd09d,
+ .short_desc = "Slot 0 of SRQ valid",
+ .long_desc = "Slot 0 of SRQ valid",
+},
+{
+ .name = "PM_MRK_DERAT_MISS_4K",
+ .code = 0x1d05c,
+ .short_desc = "Marked DERAT misses for 4K page",
+ .long_desc = "A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.",
+},
+{
+ .name = "PM_BR_MPRED_TA",
+ .code = 0x40ae,
+ .short_desc = "Branch mispredict - target address",
+ .long_desc = "A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.",
+},
+{
+ .name = "PM_INST_PTEG_FROM_L2MISS",
+ .code = 0x4e058,
+ .short_desc = "Instruction PTEG loaded from L2 miss",
+ .long_desc = "Instruction PTEG loaded from L2 miss",
+},
+{
+ .name = "PM_DPU_HELD_POWER",
+ .code = 0x20006,
+ .short_desc = "Dispatch Held due to Power Management",
+ .long_desc = "Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time",
+},
+{
+ .name = "PM_RUN_INST_CMPL",
+ .code = 0x400fa,
+ .short_desc = "Run_Instructions",
+ .long_desc = "Number of run instructions completed. ",
+},
+{
+ .name = "PM_MRK_VSU_FIN",
+ .code = 0x30032,
+ .short_desc = "vsu (fpu) marked instr finish",
+ .long_desc = "vsu (fpu) marked instr finish",
+},
+{
+ .name = "PM_LSU_SRQ_S0_VALID",
+ .code = 0xd09c,
+ .short_desc = "Slot 0 of SRQ valid",
+ .long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).",
+},
+{
+ .name = "PM_GCT_EMPTY_CYC",
+ .code = 0x20008,
+ .short_desc = "GCT empty, all threads",
+ .long_desc = "Cycles when the Global Completion Table was completely empty. No thread had an entry allocated.",
+},
+{
+ .name = "PM_IOPS_DISP",
+ .code = 0x30014,
+ .short_desc = "IOPS dispatched",
+ .long_desc = "IOPS dispatched",
+},
+{
+ .name = "PM_RUN_SPURR",
+ .code = 0x10008,
+ .short_desc = "Run SPURR",
+ .long_desc = "Run SPURR",
+},
+{
+ .name = "PM_PTEG_FROM_L21_MOD",
+ .code = 0x3c056,
+ .short_desc = "PTEG loaded from another L2 on same chip modified",
+ .long_desc = "PTEG loaded from another L2 on same chip modified",
+},
+{
+ .name = "PM_VSU0_1FLOP",
+ .code = 0xa080,
+ .short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished",
+ .long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished",
+},
+{
+ .name = "PM_SNOOP_TLBIE",
+ .code = 0xd0b2,
+ .short_desc = "TLBIE snoop",
+ .long_desc = "A tlbie was snooped from another processor.",
+},
+{
+ .name = "PM_DATA_FROM_L3MISS",
+ .code = 0x2c048,
+ .short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
+ .long_desc = "The processor's Data Cache was reloaded from beyond L3 due to a demand load",
+},
+{
+ .name = "PM_VSU_SINGLE",
+ .code = 0xa8a8,
+ .short_desc = "Vector or Scalar single precision",
+ .long_desc = "Vector or Scalar single precision",
+},
+{
+ .name = "PM_DTLB_MISS_16G",
+ .code = 0x1c05e,
+ .short_desc = "Data TLB miss for 16G page",
+ .long_desc = "Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+ .name = "PM_CMPLU_STALL_VECTOR",
+ .code = 0x2001c,
+ .short_desc = "Completion stall caused by Vector instruction",
+ .long_desc = "Completion stall caused by Vector instruction",
+},
+{
+ .name = "PM_FLUSH",
+ .code = 0x400f8,
+ .short_desc = "Flush (any type)",
+ .long_desc = "Flushes occurred including LSU and Branch flushes.",
+},
+{
+ .name = "PM_L2_LD_HIT",
+ .code = 0x36182,
+ .short_desc = "All successful load dispatches that were L2 hits",
+ .long_desc = "A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Total for all slices",
+},
+{
+ .name = "PM_NEST_PAIR2_AND",
+ .code = 0x30883,
+ .short_desc = " Nest events (MC0/MC1/PB/GX), Pair2 AND",
+ .long_desc = " Nest events (MC0/MC1/PB/GX), Pair2 AND",
+},
+{
+ .name = "PM_VSU1_1FLOP",
+ .code = 0xa082,
+ .short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished",
+ .long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished",
+},
+{
+ .name = "PM_IC_PREF_REQ",
+ .code = 0x408a,
+ .short_desc = "Instruction prefetch requests",
+ .long_desc = "An instruction prefetch request has been made.",
+},
+{
+ .name = "PM_L3_LD_HIT",
+ .code = 0x2f080,
+ .short_desc = "L3 demand LD Hits",
+ .long_desc = "L3 demand LD Hits",
+},
+{
+ .name = "PM_GCT_NOSLOT_IC_MISS",
+ .code = 0x2001a,
+ .short_desc = "GCT empty by I cache miss",
+ .long_desc = "Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.",
+},
+{
+ .name = "PM_DISP_HELD",
+ .code = 0x10006,
+ .short_desc = "Dispatch Held",
+ .long_desc = "Dispatch Held",
+},
+{
+ .name = "PM_L2_LD",
+ .code = 0x16080,
+ .short_desc = "Data Load Count",
+ .long_desc = "Data Load Count",
+},
+{
+ .name = "PM_LSU_FLUSH_SRQ",
+ .code = 0xc8bc,
+ .short_desc = "Flush: SRQ",
+ .long_desc = "Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1.",
+},
+{
+ .name = "PM_BC_PLUS_8_CONV",
+ .code = 0x40b8,
+ .short_desc = "BC+8 Converted",
+ .long_desc = "BC+8 Converted",
+},
+{
+ .name = "PM_MRK_DATA_FROM_L31_MOD_CYC",
+ .code = 0x40026,
+ .short_desc = "Marked ld latency Data source 0111 (L3.1 M same chip)",
+ .long_desc = "Marked ld latency Data source 0111 (L3.1 M same chip)",
+},
+{
+ .name = "PM_CMPLU_STALL_VECTOR_LONG",
+ .code = 0x4004a,
+ .short_desc = "completion stall due to long latency vector instruction",
+ .long_desc = "completion stall due to long latency vector instruction",
+},
+{
+ .name = "PM_L2_RCST_BUSY_RC_FULL",
+ .code = 0x26282,
+ .short_desc = " L2 activated Busy to the core for stores due to all RC full",
+ .long_desc = " L2 activated Busy to the core for stores due to all RC full",
+},
+{
+ .name = "PM_TB_BIT_TRANS",
+ .code = 0x300f8,
+ .short_desc = "Time Base bit transition",
+ .long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ",
+},
+{
+ .name = "PM_THERMAL_MAX",
+ .code = 0x40006,
+ .short_desc = "Processor In Thermal MAX",
+ .long_desc = "The processor experienced a thermal overload condition. This bit is sticky, it remains set until cleared by software.",
+},
+{
+ .name = "PM_LSU1_FLUSH_ULD",
+ .code = 0xc0b2,
+ .short_desc = "LS 1 Flush: Unaligned Load",
+ .long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).",
+},
+{
+ .name = "PM_LSU1_REJECT_LHS",
+ .code = 0xc0ae,
+ .short_desc = "LS1 Reject: Load Hit Store",
+ .long_desc = "Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.",
+},
+{
+ .name = "PM_LSU_LRQ_S0_ALLOC",
+ .code = 0xd09f,
+ .short_desc = "Slot 0 of LRQ valid",
+ .long_desc = "Slot 0 of LRQ valid",
+},
+{
+ .name = "PM_L3_CO_L31",
+ .code = 0x4f080,
+ .short_desc = "L3 Castouts to Memory",
+ .long_desc = "L3 Castouts to Memory",
+},
+{
+ .name = "PM_POWER_EVENT4",
+ .code = 0x4006e,
+ .short_desc = "Power Management Event 4",
+ .long_desc = "Power Management Event 4",
+},
+{
+ .name = "PM_DATA_FROM_L31_SHR",
+ .code = 0x1c04e,
+ .short_desc = "Data loaded from another L3 on same chip shared",
+ .long_desc = "Data loaded from another L3 on same chip shared",
+},
+{
+ .name = "PM_BR_UNCOND",
+ .code = 0x409e,
+ .short_desc = "Unconditional Branch",
+ .long_desc = "An unconditional branch was executed.",
+},
+{
+ .name = "PM_LSU1_DC_PREF_STREAM_ALLOC",
+ .code = 0xd0aa,
+ .short_desc = "LS 1 D cache new prefetch stream allocated",
+ .long_desc = "LS 1 D cache new prefetch stream allocated",
+},
+{
+ .name = "PM_PMC4_REWIND",
+ .code = 0x10020,
+ .short_desc = "PMC4 Rewind Event",
+ .long_desc = "PMC4 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.",
+},
+{
+ .name = "PM_L2_RCLD_DISP",
+ .code = 0x16280,
+ .short_desc = " L2 RC load dispatch attempt",
+ .long_desc = " L2 RC load dispatch attempt",
+},
+{
+ .name = "PM_THRD_PRIO_2_3_CYC",
+ .code = 0x40b2,
+ .short_desc = " Cycles thread running at priority level 2 or 3",
+ .long_desc = " Cycles thread running at priority level 2 or 3",
+},
+{
+ .name = "PM_MRK_PTEG_FROM_L2MISS",
+ .code = 0x4d058,
+ .short_desc = "Marked PTEG loaded from L2 miss",
+ .long_desc = "A Page Table Entry was loaded into the ERAT but not from the local L2 due to a marked load or store.",
+},
+{
+ .name = "PM_IC_DEMAND_L2_BHT_REDIRECT",
+ .code = 0x4098,
+ .short_desc = " L2 I cache demand request due to BHT redirect",
+ .long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).",
+},
+{
+ .name = "PM_LSU_DERAT_MISS",
+ .code = 0x200f6,
+ .short_desc = "DERAT Reloaded due to a DERAT miss",
+ .long_desc = "Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.",
+},
+{
+ .name = "PM_IC_PREF_CANCEL_L2",
+ .code = 0x4094,
+ .short_desc = "L2 Squashed request",
+ .long_desc = "L2 Squashed request",
+},
+{
+ .name = "PM_MRK_FIN_STALL_CYC_COUNT",
+ .code = 0x1003d,
+ .short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)",
+ .long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)",
+},
+{
+ .name = "PM_BR_PRED_CCACHE",
+ .code = 0x40a0,
+ .short_desc = "Count Cache Predictions",
+ .long_desc = "The count value of a Branch and Count instruction was predicted",
+},
+{
+ .name = "PM_GCT_UTIL_1_TO_2_SLOTS",
+ .code = 0x209c,
+ .short_desc = "GCT Utilization 1-2 entries",
+ .long_desc = "GCT Utilization 1-2 entries",
+},
+{
+ .name = "PM_MRK_ST_CMPL_INT",
+ .code = 0x30034,
+ .short_desc = "marked store complete (data home) with intervention",
+ .long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention",
+},
+{
+ .name = "PM_LSU_TWO_TABLEWALK_CYC",
+ .code = 0xd0a6,
+ .short_desc = "Cycles when two tablewalks pending on this thread",
+ .long_desc = "Cycles when two tablewalks pending on this thread",
+},
+{
+ .name = "PM_MRK_DATA_FROM_L3MISS",
+ .code = 0x2d048,
+ .short_desc = "Marked data loaded from L3 miss",
+ .long_desc = "DL1 was reloaded from beyond L3 due to a marked load.",
+},
+{
+ .name = "PM_GCT_NOSLOT_CYC",
+ .code = 0x100f8,
+ .short_desc = "No itags assigned ",
+ .long_desc = "Cycles when the Global Completion Table has no slots from this thread.",
+},
+{
+ .name = "PM_LSU_SET_MPRED",
+ .code = 0xc0a8,
+ .short_desc = "Line already in cache at reload time",
+ .long_desc = "Line already in cache at reload time",
+},
+{
+ .name = "PM_FLUSH_DISP_TLBIE",
+ .code = 0x208a,
+ .short_desc = "Dispatch Flush: TLBIE",
+ .long_desc = "Dispatch Flush: TLBIE",
+},
+{
+ .name = "PM_VSU1_FCONV",
+ .code = 0xa0b2,
+ .short_desc = "Convert instruction executed",
+ .long_desc = "Convert instruction executed",
+},
+{
+ .name = "PM_DERAT_MISS_16G",
+ .code = 0x4c05c,
+ .short_desc = "DERAT misses for 16G page",
+ .long_desc = "A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.",
+},
+{
+ .name = "PM_INST_FROM_LMEM",
+ .code = 0x3404a,
+ .short_desc = "Instruction fetched from local memory",
+ .long_desc = "An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions",
+},
+{
+ .name = "PM_IC_DEMAND_L2_BR_REDIRECT",
+ .code = 0x409a,
+ .short_desc = " L2 I cache demand request due to branch redirect",
+ .long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).",
+},
+{
+ .name = "PM_CMPLU_STALL_SCALAR_LONG",
+ .code = 0x20018,
+ .short_desc = "Completion stall caused by long latency scalar instruction",
+ .long_desc = "Completion stall caused by long latency scalar instruction",
+},
+{
+ .name = "PM_INST_PTEG_FROM_L2",
+ .code = 0x1e050,
+ .short_desc = "Instruction PTEG loaded from L2",
+ .long_desc = "Instruction PTEG loaded from L2",
+},
+{
+ .name = "PM_PTEG_FROM_L2",
+ .code = 0x1c050,
+ .short_desc = "PTEG loaded from L2",
+ .long_desc = "A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.",
+},
+{
+ .name = "PM_MRK_DATA_FROM_L21_SHR_CYC",
+ .code = 0x20024,
+ .short_desc = "Marked ld latency Data source 0100 (L2.1 S)",
+ .long_desc = "Marked load latency Data source 0100 (L2.1 S)",
+},
+{
+ .name = "PM_MRK_DTLB_MISS_4K",
+ .code = 0x2d05a,
+ .short_desc = "Marked Data TLB misses for 4K page",
+ .long_desc = "Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+ .name = "PM_VSU0_FPSCR",
+ .code = 0xb09c,
+ .short_desc = "Move to/from FPSCR type instruction issued on Pipe 0",
+ .long_desc = "Move to/from FPSCR type instruction issued on Pipe 0",
+},
+{
+ .name = "PM_VSU1_VECT_DOUBLE_ISSUED",
+ .code = 0xb082,
+ .short_desc = "Double Precision vector instruction issued on Pipe1",
+ .long_desc = "Double Precision vector instruction issued on Pipe1",
+},
+{
+ .name = "PM_MRK_PTEG_FROM_RL2L3_MOD",
+ .code = 0x1d052,
+ .short_desc = "Marked PTEG loaded from remote L2 or L3 modified",
+ .long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load or store.",
+},
+{
+ .name = "PM_MEM0_RQ_DISP",
+ .code = 0x10083,
+ .short_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit1",
+ .long_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit1",
+},
+{
+ .name = "PM_L2_LD_MISS",
+ .code = 0x26080,
+ .short_desc = "Data Load Miss",
+ .long_desc = "Data Load Miss",
+},
+{
+ .name = "PM_VMX_RESULT_SAT_1",
+ .code = 0xb0a0,
+ .short_desc = "Valid result with sat=1",
+ .long_desc = "Valid result with sat=1",
+},
+{
+ .name = "PM_L1_PREF",
+ .code = 0xd8b8,
+ .short_desc = "L1 Prefetches",
+ .long_desc = "A request to prefetch data into the L1 was made",
+},
+{
+ .name = "PM_MRK_DATA_FROM_LMEM_CYC",
+ .code = 0x2002c,
+ .short_desc = "Marked ld latency Data Source 1100 (Local Memory)",
+ .long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.",
+},
+{
+ .name = "PM_GRP_IC_MISS_NONSPEC",
+ .code = 0x1000c,
+ .short_desc = "Group experienced non-speculative I cache miss",
+ .long_desc = "Number of groups, counted at completion, that have encountered an instruction cache miss.",
+},
+{
+ .name = "PM_PB_NODE_PUMP",
+ .code = 0x10081,
+ .short_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit0",
+ .long_desc = " Nest events (MC0/MC1/PB/GX), Pair0 Bit0",
+},
+{
+ .name = "PM_SHL_MERGED",
+ .code = 0x5084,
+ .short_desc = "SHL table entry merged with existing",
+ .long_desc = "SHL table entry merged with existing",
+},
+{
+ .name = "PM_NEST_PAIR1_ADD",
+ .code = 0x20881,
+ .short_desc = " Nest events (MC0/MC1/PB/GX), Pair1 ADD",
+ .long_desc = " Nest events (MC0/MC1/PB/GX), Pair1 ADD",
+},
+{
+ .name = "PM_DATA_FROM_L3",
+ .code = 0x1c048,
+ .short_desc = "Data loaded from L3",
+ .long_desc = "The processor's Data Cache was reloaded from the local L3 due to a demand load.",
+},
+{
+ .name = "PM_LSU_FLUSH",
+ .code = 0x208e,
+ .short_desc = "Flush initiated by LSU",
+ .long_desc = "A flush was initiated by the Load Store Unit.",
+},
+{
+ .name = "PM_LSU_SRQ_SYNC_COUNT",
+ .code = 0xd097,
+ .short_desc = "SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)",
+ .long_desc = "SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)",
+},
+{
+ .name = "PM_PMC2_OVERFLOW",
+ .code = 0x30010,
+ .short_desc = "Overflow from counter 2",
+ .long_desc = "Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+},
+{
+ .name = "PM_LSU_LDF",
+ .code = 0xc884,
+ .short_desc = "All Scalar Loads",
+ .long_desc = "LSU executed Floating Point load instruction. Combined Unit 0 + 1.",
+},
+{
+ .name = "PM_POWER_EVENT3",
+ .code = 0x3006e,
+ .short_desc = "Power Management Event 3",
+ .long_desc = "Power Management Event 3",
+},
+{
+ .name = "PM_DISP_WT",
+ .code = 0x30008,
+ .short_desc = "Dispatched Starved (not held, nothing to dispatch)",
+ .long_desc = "Dispatched Starved (not held, nothing to dispatch)",
+},
+{
+ .name = "PM_CMPLU_STALL_REJECT",
+ .code = 0x40016,
+ .short_desc = "Completion stall caused by reject",
+ .long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.",
+},
+{
+ .name = "PM_IC_BANK_CONFLICT",
+ .code = 0x4082,
+ .short_desc = "Read blocked due to interleave conflict. ",
+ .long_desc = "Read blocked due to interleave conflict. ",
+},
+{
+ .name = "PM_BR_MPRED_CR_TA",
+ .code = 0x48ae,
+ .short_desc = "Branch mispredict - taken/not taken and target",
+ .long_desc = "Branch mispredict - taken/not taken and target",
+},
+{
+ .name = "PM_L2_INST_MISS",
+ .code = 0x36082,
+ .short_desc = "Instruction Load Misses",
+ .long_desc = "Instruction Load Misses",
+},
+{
+ .name = "PM_CMPLU_STALL_ERAT_MISS",
+ .code = 0x40018,
+ .short_desc = "Completion stall caused by ERAT miss",
+ .long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT.",
+},
+{
+ .name = "PM_NEST_PAIR2_ADD",
+ .code = 0x30881,
+ .short_desc = " Nest events (MC0/MC1/PB/GX), Pair2 ADD",
+ .long_desc = " Nest events (MC0/MC1/PB/GX), Pair2 ADD",
+},
+{
+ .name = "PM_MRK_LSU_FLUSH",
+ .code = 0xd08c,
+ .short_desc = "Flush: (marked) : All Cases",
+ .long_desc = "Marked flush initiated by LSU",
+},
+{
+ .name = "PM_L2_LDST",
+ .code = 0x16880,
+ .short_desc = "Data Load+Store Count",
+ .long_desc = "Data Load+Store Count",
+},
+{
+ .name = "PM_INST_FROM_L31_SHR",
+ .code = 0x1404e,
+ .short_desc = "Instruction fetched from another L3 on same chip shared",
+ .long_desc = "Instruction fetched from another L3 on same chip shared",
+},
+{
+ .name = "PM_VSU0_FIN",
+ .code = 0xa0bc,
+ .short_desc = "VSU0 Finished an instruction",
+ .long_desc = "VSU0 Finished an instruction",
+},
+{
+ .name = "PM_LARX_LSU",
+ .code = 0xc894,
+ .short_desc = "Larx Finished",
+ .long_desc = "Larx Finished",
+},
+{
+ .name = "PM_INST_FROM_RMEM",
+ .code = 0x34042,
+ .short_desc = "Instruction fetched from remote memory",
+ .long_desc = "An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions",
+},
+{
+ .name = "PM_DISP_CLB_HELD_TLBIE",
+ .code = 0x2096,
+ .short_desc = "Dispatch Hold: Due to TLBIE",
+ .long_desc = "Dispatch Hold: Due to TLBIE",
+},
+{
+ .name = "PM_MRK_DATA_FROM_DMEM_CYC",
+ .code = 0x2002e,
+ .short_desc = "Marked ld latency Data Source 1110 (Distant Memory)",
+ .long_desc = "Marked ld latency Data Source 1110 (Distant Memory)",
+},
+{
+ .name = "PM_BR_PRED_CR",
+ .code = 0x40a8,
+ .short_desc = "Branch predict - taken/not taken",
+ .long_desc = "A conditional branch instruction was predicted as taken or not taken.",
+},
+{
+ .name = "PM_LSU_REJECT",
+ .code = 0x10064,
+ .short_desc = "LSU Reject (up to 2 per cycle)",
+ .long_desc = "The Load Store Unit rejected an instruction. Combined Unit 0 + 1",
+},
+{
+ .name = "PM_GCT_UTIL_3_TO_6_SLOTS",
+ .code = 0x209e,
+ .short_desc = "GCT Utilization 3-6 entries",
+ .long_desc = "GCT Utilization 3-6 entries",
+},
+{
+ .name = "PM_CMPLU_STALL_END_GCT_NOSLOT",
+ .code = 0x10028,
+ .short_desc = "Count ended because GCT went empty",
+ .long_desc = "Count ended because GCT went empty",
+},
+{
+ .name = "PM_LSU0_REJECT_LMQ_FULL",
+ .code = 0xc0a4,
+ .short_desc = "LS0 Reject: LMQ Full (LHR)",
+ .long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.",
+},
+{
+ .name = "PM_VSU_FEST",
+ .code = 0xa8b8,
+ .short_desc = "Estimate instruction executed",
+ .long_desc = "Estimate instruction executed",
+},
+{
+ .name = "PM_NEST_PAIR0_AND",
+ .code = 0x10883,
+ .short_desc = " Nest events (MC0/MC1/PB/GX), Pair0 AND",
+ .long_desc = " Nest events (MC0/MC1/PB/GX), Pair0 AND",
+},
+{
+ .name = "PM_PTEG_FROM_L3",
+ .code = 0x2c050,
+ .short_desc = "PTEG loaded from L3",
+ .long_desc = "A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.",
+},
+{
+ .name = "PM_POWER_EVENT2",
+ .code = 0x2006e,
+ .short_desc = "Power Management Event 2",
+ .long_desc = "Power Management Event 2",
+},
+{
+ .name = "PM_IC_PREF_CANCEL_PAGE",
+ .code = 0x4090,
+ .short_desc = "Prefetch Canceled due to page boundary",
+ .long_desc = "Prefetch Canceled due to page boundary",
+},
+{
+ .name = "PM_VSU0_FSQRT_FDIV",
+ .code = 0xa088,
+ .short_desc = "four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!",
+ .long_desc = "four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!",
+},
+{
+ .name = "PM_MRK_GRP_CMPL",
+ .code = 0x40030,
+ .short_desc = "Marked group complete",
+ .long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.",
+},
+{
+ .name = "PM_VSU0_SCAL_DOUBLE_ISSUED",
+ .code = 0xb088,
+ .short_desc = "Double Precision scalar instruction issued on Pipe0",
+ .long_desc = "Double Precision scalar instruction issued on Pipe0",
+},
+{
+ .name = "PM_GRP_DISP",
+ .code = 0x3000a,
+ .short_desc = "dispatch_success (Group Dispatched)",
+ .long_desc = "A group was dispatched",
+},
+{
+ .name = "PM_LSU0_LDX",
+ .code = 0xc088,
+ .short_desc = "LS0 Vector Loads",
+ .long_desc = "LS0 Vector Loads",
+},
+{
+ .name = "PM_DATA_FROM_L2",
+ .code = 0x1c040,
+ .short_desc = "Data loaded from L2",
+ .long_desc = "The processor's Data Cache was reloaded from the local L2 due to a demand load.",
+},
+{
+ .name = "PM_MRK_DATA_FROM_RL2L3_MOD",
+ .code = 0x1d042,
+ .short_desc = "Marked data loaded from remote L2 or L3 modified",
+ .long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a marked load.",
+},
+{
+ .name = "PM_LD_REF_L1",
+ .code = 0xc880,
+ .short_desc = " L1 D cache load references counted at finish",
+ .long_desc = " L1 D cache load references counted at finish",
+},
+{
+ .name = "PM_VSU0_VECT_DOUBLE_ISSUED",
+ .code = 0xb080,
+ .short_desc = "Double Precision vector instruction issued on Pipe0",
+ .long_desc = "Double Precision vector instruction issued on Pipe0",
+},
+{
+ .name = "PM_VSU1_2FLOP_DOUBLE",
+ .code = 0xa08e,
+ .short_desc = "two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ",
+ .long_desc = "two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp) ",
+},
+{
+ .name = "PM_THRD_PRIO_6_7_CYC",
+ .code = 0x40b6,
+ .short_desc = " Cycles thread running at priority level 6 or 7",
+ .long_desc = " Cycles thread running at priority level 6 or 7",
+},
+{
+ .name = "PM_BC_PLUS_8_RSLV_TAKEN",
+ .code = 0x40ba,
+ .short_desc = "BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled",
+ .long_desc = "BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled",
+},
+{
+ .name = "PM_BR_MPRED_CR",
+ .code = 0x40ac,
+ .short_desc = "Branch mispredict - taken/not taken",
+ .long_desc = "A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.",
+},
+{
+ .name = "PM_L3_CO_MEM",
+ .code = 0x4f082,
+ .short_desc = "L3 Castouts to L3.1",
+ .long_desc = "L3 Castouts to L3.1",
+},
+{
+ .name = "PM_LD_MISS_L1",
+ .code = 0x400f0,
+ .short_desc = "Load Missed L1",
+ .long_desc = "Load references that miss the Level 1 Data cache. Combined unit 0 + 1.",
+},
+{
+ .name = "PM_DATA_FROM_RL2L3_MOD",
+ .code = 0x1c042,
+ .short_desc = "Data loaded from remote L2 or L3 modified",
+ .long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load",
+},
+{
+ .name = "PM_LSU_SRQ_FULL_CYC",
+ .code = 0x1001a,
+ .short_desc = "Storage Queue is full and is blocking dispatch",
+ .long_desc = "Cycles the Store Request Queue is full.",
+},
+{
+ .name = "PM_TABLEWALK_CYC",
+ .code = 0x10026,
+ .short_desc = "Cycles when a tablewalk (I or D) is active",
+ .long_desc = "Cycles doing instruction or data tablewalks",
+},
+{
+ .name = "PM_MRK_PTEG_FROM_RMEM",
+ .code = 0x3d052,
+ .short_desc = "Marked PTEG loaded from remote memory",
+ .long_desc = "A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB",
+},
+{
+ .name = "PM_LSU_SRQ_STFWD",
+ .code = 0xc8a0,
+ .short_desc = "Load got data from a store",
+ .long_desc = "Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.",
+},
+{
+ .name = "PM_INST_PTEG_FROM_RMEM",
+ .code = 0x3e052,
+ .short_desc = "Instruction PTEG loaded from remote memory",
+ .long_desc = "Instruction PTEG loaded from remote memory",
+},
+{
+ .name = "PM_FXU0_FIN",
+ .code = 0x10004,
+ .short_desc = "FXU0 Finished",
+ .long_desc = "The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.",
+},
+{
+ .name = "PM_LSU1_L1_SW_PREF",
+ .code = 0xc09e,
+ .short_desc = "LSU1 Software L1 Prefetches, including SW Transient Prefetches",
+ .long_desc = "LSU1 Software L1 Prefetches, including SW Transient Prefetches",
+},
+{
+ .name = "PM_PTEG_FROM_L31_MOD",
+ .code = 0x1c054,
+ .short_desc = "PTEG loaded from another L3 on same chip modified",
+ .long_desc = "PTEG loaded from another L3 on same chip modified",
+},
+{
+ .name = "PM_PMC5_OVERFLOW",
+ .code = 0x10024,
+ .short_desc = "Overflow from counter 5",
+ .long_desc = "Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.",
+},
+{
+ .name = "PM_LD_REF_L1_LSU1",
+ .code = 0xc082,
+ .short_desc = "LS1 L1 D cache load references counted at finish",
+ .long_desc = "Load references to Level 1 Data Cache, by unit 1.",
+},
+{
+ .name = "PM_INST_PTEG_FROM_L21_SHR",
+ .code = 0x4e056,
+ .short_desc = "Instruction PTEG loaded from another L2 on same chip shared",
+ .long_desc = "Instruction PTEG loaded from another L2 on same chip shared",
+},
+{
+ .name = "PM_CMPLU_STALL_THRD",
+ .code = 0x1001c,
+ .short_desc = "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn",
+ .long_desc = "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn",
+},
+{
+ .name = "PM_DATA_FROM_RMEM",
+ .code = 0x3c042,
+ .short_desc = "Data loaded from remote memory",
+ .long_desc = "The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.",
+},
+{
+ .name = "PM_VSU0_SCAL_SINGLE_ISSUED",
+ .code = 0xb084,
+ .short_desc = "Single Precision scalar instruction issued on Pipe0",
+ .long_desc = "Single Precision scalar instruction issued on Pipe0",
+},
+{
+ .name = "PM_BR_MPRED_LSTACK",
+ .code = 0x40a6,
+ .short_desc = "Branch Mispredict due to Link Stack",
+ .long_desc = "Branch Mispredict due to Link Stack",
+},
+{
+ .name = "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
+ .code = 0x40028,
+ .short_desc = "Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)",
+ .long_desc = "Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)",
+},
+{
+ .name = "PM_LSU0_FLUSH_UST",
+ .code = 0xc0b4,
+ .short_desc = "LS0 Flush: Unaligned Store",
+ .long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).",
+},
+{
+ .name = "PM_LSU_NCST",
+ .code = 0xc090,
+ .short_desc = "Non-cachable Stores sent to nest",
+ .long_desc = "Non-cachable Stores sent to nest",
+},
+{
+ .name = "PM_BR_TAKEN",
+ .code = 0x20004,
+ .short_desc = "Branch Taken",
+ .long_desc = "A branch instruction was taken. This could have been a conditional branch or an unconditional branch",
+},
+{
+ .name = "PM_INST_PTEG_FROM_LMEM",
+ .code = 0x4e052,
+ .short_desc = "Instruction PTEG loaded from local memory",
+ .long_desc = "Instruction PTEG loaded from local memory",
+},
+{
+ .name = "PM_GCT_NOSLOT_BR_MPRED_IC_MISS",
+ .code = 0x4001c,
+ .short_desc = "GCT empty by branch mispredict + IC miss",
+ .long_desc = "No slot in GCT caused by branch mispredict or I cache miss",
+},
+{
+ .name = "PM_DTLB_MISS_4K",
+ .code = 0x2c05a,
+ .short_desc = "Data TLB miss for 4K page",
+ .long_desc = "Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.",
+},
+{
+ .name = "PM_PMC4_SAVED",
+ .code = 0x30022,
+ .short_desc = "PMC4 Rewind Value saved (matched condition)",
+ .long_desc = "PMC4 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.",
+},
+{
+ .name = "PM_VSU1_PERMUTE_ISSUED",
+ .code = 0xb092,
+ .short_desc = "Permute VMX Instruction Issued",
+ .long_desc = "Permute VMX Instruction Issued",
+},
+{
+ .name = "PM_SLB_MISS",
+ .code = 0xd890,
+ .short_desc = "Data + Instruction SLB Miss - Total of all segment sizes",
+ .long_desc = "Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.",
+},
+{
+ .name = "PM_LSU1_FLUSH_LRQ",
+ .code = 0xc0ba,
+ .short_desc = "LS1 Flush: LRQ",
+ .long_desc = "Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.",
+},
+{
+ .name = "PM_DTLB_MISS",
+ .code = 0x300fc,
+ .short_desc = "TLB reload valid",
+ .long_desc = "Data TLB misses, all page sizes.",
+},
+{
+ .name = "PM_VSU1_FRSP",
+ .code = 0xa0b6,
+ .short_desc = "Round to single precision instruction executed",
+ .long_desc = "Round to single precision instruction executed",
+},
+{
+ .name = "PM_VSU_VECTOR_DOUBLE_ISSUED",
+ .code = 0xb880,
+ .short_desc = "Double Precision vector instruction issued on Pipe0",
+ .long_desc = "Double Precision vector instruction issued on Pipe0",
+},
+{
+ .name = "PM_L2_CASTOUT_SHR",
+ .code = 0x16182,
+ .short_desc = "L2 Castouts - Shared (T, Te, Si, S)",
+ .long_desc = "An L2 line in the Shared state was castout. Total for all slices.",
+},
+{
+ .name = "PM_DATA_FROM_DL2L3_SHR",
+ .code = 0x3c04