How do you test your USB 3.0 Host or Hub in the lab? Do rely solely on off the shelf devices available in the market? Read ahead to know why this might not be a good idea.
The USB 3.0 protocol is much more complicated than the USB 2.0 protocol. The additional complexity arises mainly due to two factors: high level of concurrency/parallelism and elaborate error recovery mechanisms.
The USB 3.0 protocol has been designed to support a high level of concurrency and parallelism. The USB 3.0 bus is full duplex and packets for different endpoints can be interleaved. Due to this parallelism, the controller complexity increases due as the number of possible traffic scenarios increases.
Also, the protocol allows data transfers at 5Gbps through a cable (a ~10x improvement over USB2). This "SuperSpeed" rate implies a bit time of just 200ps. Thus, noise and other signal integrity effects play a major role and the probability of data corruption on the bus is higher. The protocol allows for graceful recovery from such errors and provides error recovery mechanisms in all hardware and software layers. These error recovery mechanisms also add to the complexity of the USB 3.0 Host and Hub controllers.
Off the shelf devices (such as hard disks, web-cams, flash-drives, keyboard, mice etc) do not provide coverage for these two aspects that make USB 3.0 a complicated protocol. Since most of these off the shelf devices were designed for the legacy USB 2.0 protocol, their class drivers do not perform any concurrent transfers to different endpoints and also do not perform any concurrent IN and OUT transfers.
And of course, off the shelf devices do not inject errors such as CRC errors, packet framing errors, endpoint STALLs etc.
USB 3.0 requires more detailed and thorough lab testing. Simulation verification is not enough as the USB 3.0 host/hub design can be exposed to only a few microseconds worth of traffic. Also, in simulation, the testing environment is synthetic and the controller is not interacting with real software, real analog PHY etc.
Arrow Devices' USB Validator Traffic Exerciser is a effort to bridge this gap. It allows teams working on USB 3.0 based designs to quickly check various traffic and error injection cases on their FPGA or silicon prototypes. Bugs that could have sneaked past into production silicon can be caught and fixed thus lowering the risk to the final SOC.
To know more, please email us at contact@arrowdevices.com