Province: Karnataka
Description:
Job ID: JR0813457
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire
IP Logic Validation Lead
In this Role, you will be the technical lead in defining and developing a new
Serial IO or parallel IO PHY Logic architecture, you will define and develop
cutting edge designs for high speed protocols as USB, PCI Express or MIPI
using leading edge process nodes. Interact and take part in in protocol
development, spec definition and implementation of the PHYs. In this job role,
you will get opportunity to supervise, guide, and coordinate the junior
engineer.
Qualifications
Qualifications – 10-12 years of experience in high-speed serial PHY design
with MSEE or PhD degree – Deep understanding of industry standard protocols
such as MIPI or DDR – Experience and knowledge of PCS protocol or PHY
interface protocol. Knowledge and experience of Logic architecture of PHY,
tradeoffs, performance parameters – Deep understanding in high speed Data path
logic Design, CDR, clocking, and circuit adaptation schemes – Experience in
analyzing link budget for high-speed serial links – Knowledgeable with high-
speed serial data protocols (as USB, PCI Express, SATA, MIPI) – Excellent
communication skills
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design,
development, and production of system-on-a-chip (SoC) products that go into
Intel’s generation client and mobile platforms. PEG strives to lead the
industry moving forward through product innovation and world class
engineering.
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