I used Xilinx products many years ago and I am just starting to get back into VHDL/FPGAs/Xilinx and it has been great fun so far but there are a couple of quick questions which I'm sure will be answered very easily buy some of you on here.
1. I have generated my project in VHDL but I would like to add that code to a Schematic, I knwo it can be done, I've generated the symbol but I'm not sure how to export that to a Schematic?
2. In my VHDL code I have a number of inputs and a number of outputs. I have the file set up as a basic counter and then a series of functions are applied to the count value. Now currently I have the inputs which are correct and two set of outputs, but I only want one set to be assigned to a pin. Is it possible to declare them as a variable rather than output so it is not assigned to a pin?
Thanks in advance for your help.
Richard