Hi all,
I am building a MicroBlaze design on Spartan6-xl150 containing an Soft-TEMAC (I do have a license) and some selfdefined components. On 13.2 everything worked fine.
system_ethernet_wrapper_xst.srp contains NO errors.
Whats wrong?
---------------------------------------------------------------------------------------------------------------
Windows SystemLOG:
Name der fehlerhaften Anwendung: xst.exe, Version: 0.0.0.0, Zeitstempel: 0x51b3ab27
Name des fehlerhaften Moduls: libSecurity_FNP.dll, Version: 11.11.0.0, Zeitstempel: 0x50116b0b
Ausnahmecode: 0xc0000005
Fehleroffset: 0x0000000000001a52
ID des fehlerhaften Prozesses: 0x1c1c
Startzeit der fehlerhaften Anwendung: 0x01ce91b0b07cf089
Pfad der fehlerhaften Anwendung: e:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\xst.exe
Pfad des fehlerhaften Moduls: e:\Xilinx\14.6\ISE_DS\ISE\lib\nt64\libSecurity_FNP.dll
Berichtskennung: da139af6-fda4-11e2-92d1-0022b071f8c7
---------------------------------------------------------------------------------------------------------------
XPS -> Export Design to SDK:
Copied E:/Xilinx/14.6/ISE_DS/EDK/data/xflow/bitgen_spartan6.ut to etc directory
Copied file E:/Xilinx/14.6/ISE_DS/EDK/data/xflow/fast_runtime_spartan6.opt to etc directory
INFO:coreutil - Full license for component <axi_ethernet_soft_tri_mode> allows you to use this component. This license does not give you access to source code implementing this component.
The license for this core was generated for XXXX.YYYY@ZZZZ.com on 07/17/2013It is the responsibility of the Licensee of this core to adhere to all terms and conditions of the applicable license agreement when using this core.
********************************************************************************
At Local date and time: Mon Aug 05 13:16:58 2013
make -f system.make exporttosdk started...
IF NOT EXIST "SDK\SDK_Export\hw" @mkdir "SDK\SDK_Export\hw"
psf2Edward -inp system.xmp -exit_on_error -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK\SDK_Export\hw/system.xml
Release 14.6 - psf2Edward EDK_P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi4_0 - 6 master(s) : 3 slave(s)
IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 16 slave(s)
IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s)
IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s)
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 13
slave(s)
Checking port drivers...
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4_0.
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Invoking MIG ...
MIG returned 0
Invoking MIG ...
MIG returned 0
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
INTC INFO:: Processor_clk not connected.. IRQ to Microblaze is generated on AXI
clock.
Conversion to XML complete.
xdsgen -inp system.xmp -report SDK\SDK_Export\hw/system.html -make_docs_local
Release 14.6 - xdsgen EDK_P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Generated Block Diagram.
Rasterizing axi4_0.jpg.....
Rasterizing axi4lite_0.jpg.....
Rasterizing microblaze_0.jpg.....
Rasterizing microblaze_0_ilmb.jpg.....
Rasterizing microblaze_0_dlmb.jpg.....
Rasterizing microblaze_0_i_bram_ctrl.jpg.....
Rasterizing microblaze_0_d_bram_ctrl.jpg.....
Rasterizing microblaze_0_bram_block.jpg.....
Rasterizing proc_sys_reset_0.jpg.....
Rasterizing clock_generator_0.jpg.....
Rasterizing clock_generator_1.jpg.....
Rasterizing debug_module.jpg.....
Rasterizing UART.jpg.....
Rasterizing MCB3_DDR3.jpg.....
Rasterizing MCB1_DDR3.jpg.....
Rasterizing Ethernet.jpg.....
Rasterizing axi_timer_0.jpg.....
Rasterizing Ethernet_dma.jpg.....
Rasterizing microblaze_0_intc.jpg.....
Rasterizing axi_uart16550_0.jpg.....
Rasterizing axi_uart16550_1.jpg.....
Rasterizing axi_uart16550_2.jpg.....
Rasterizing axi_uart16550_3.jpg.....
Rasterizing axi_uart16550_4.jpg.....
Rasterizing axi_uart16550_5.jpg.....
Rasterizing axi_uart16550_6.jpg.....
Rasterizing axi_spi_0.jpg.....
Rasterizing axi2axi_connector_1.jpg.....
Rasterizing axi_interconnect_1.jpg.....
Rasterizing axi_timer_1.jpg.....
Rasterizing axi_gpio_0.jpg.....
Rasterizing axi_gpio_1.jpg.....
Rasterizing axi_spi_1.jpg.....
Rasterizing axi_spi_2.jpg.....
Rasterizing axi_spi_3.jpg.....
Rasterizing axi_spi_4.jpg.....
Rasterizing axi_spi_5.jpg.....
Rasterizing axi_epc_0.jpg.....
Rasterizing axi_cdma_0.jpg.....
Rasterizing system_blkd.jpg.....
Report generated.
Report generation completed.
"****************************************************"
"Creating system netlist for hardware specification.."
"****************************************************"
platgen -p xc6slx150fgg484-3 -lang vhdl -intstyle default -msg __xps/ise/xmsgprops.lst system.mhs
Release 14.6 - platgen Xilinx EDK 14.6 Build EDK_P.68d
(nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: platgen -p xc6slx150fgg484-3 -lang vhdl -intstyle default -msg
__xps/ise/xmsgprops.lst system.mhs
Parse E:/projects/DoLOG_146/FPGATransmitter/system.mhs ...
Read MPD definitions ...
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4_0 - tcl is overriding
PARAMETER C_BASEFAMILY value to spartan6 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_
06_a\data\axi_interconnect_v2_1_0.mpd line 81
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is
overriding PARAMETER C_BASEFAMILY value to spartan6 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_
06_a\data\axi_interconnect_v2_1_0.mpd line 81
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_ENDIANNESS value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 198
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_ICACHE_USE_FSL value to 0 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 339
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_DCACHE_USE_FSL value to 0 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 369
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_DCACHE_INTERFACE value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 372
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB3_DDR3 - tcl is overriding
PARAMETER C_SYS_RST_PRESENT value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 239
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB1_DDR3 - tcl is overriding
PARAMETER C_SYS_RST_PRESENT value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 239
Device number is xc6slx150
INFO:EDK:4130 - IPNAME: axi_ethernet, INSTANCE:Ethernet - tcl is overriding
PARAMETER C_DEVICE value to xc6slx150 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_ethernet_v3_01_a
\data\axi_ethernet_v2_1_0.mpd line 99
INFO:EDK:4130 - IPNAME: axi_ethernet, INSTANCE:Ethernet - tcl is overriding
PARAMETER C_USE_GTH value to 0 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_ethernet_v3_01_a
\data\axi_ethernet_v2_1_0.mpd line 112
INFO:EDK:4130 - IPNAME: axi_intc, INSTANCE:microblaze_0_intc - tcl is overriding
PARAMETER C_NUM_INTR_INPUTS value to 24 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 85
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to spartan6 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_
06_a\data\axi_interconnect_v2_1_0.mpd line 81
INFO:EDK:4130 - IPNAME: axi_cdma, INSTANCE:axi_cdma_0 - tcl is overriding
PARAMETER C_INTERCONNECT_M_AXI_WRITE_ISSUING value to 8 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_cdma_v3_04_a\dat
a\axi_cdma_v2_1_0.mpd line 119
INFO:EDK:4130 - IPNAME: axi_cdma, INSTANCE:axi_cdma_0 - tcl is overriding
PARAMETER C_INTERCONNECT_M_AXI_READ_ISSUING value to 8 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_cdma_v3_04_a\dat
a\axi_cdma_v2_1_0.mpd line 117
INFO:EDK:4130 - IPNAME: axi_cdma, INSTANCE:axi_cdma_0 - tcl is overriding
PARAMETER C_AXI_LITE_IS_ASYNC value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_cdma_v3_04_a\dat
a\axi_cdma_v2_1_0.mpd line 82
Computing clock values...
INFO:EDK:740 - Cannot determine the input clock associated with port :
microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this
core and cores connected to it.
INFO:EDK:740 - Cannot determine the input clock associated with port :
microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this
core and cores connected to it.
INFO:EDK:1039 - Did not update the value for parameter:
axi_epc_0:C_PRH_CLK_PERIOD_PS. Top-level frequency could not be propagated to
this IP. Please make sure that you have specified the frequency of the
top-level clock port, and that the clocks are properly connected.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0000000000-0x0000ffff) microblaze_0_d_bram_ctrl microblaze_0_dlmb
(0000000000-0x0000ffff) microblaze_0_i_bram_ctrl microblaze_0_ilmb
(0x40000000-0x4000ffff)
axi_gpio_1 axi4lite_0->axi2axi_connector_1->axi_interconnect_1
(0x40020000-0x4002ffff)
axi_gpio_0 axi4lite_0->axi2axi_connector_1->axi_interconnect_1
(0x40400000-0x4040ffff) axi_uart16550_6 axi4lite_0
(0x40420000-0x4042ffff) axi_uart16550_5 axi4lite_0
(0x40440000-0x4044ffff) axi_uart16550_4 axi4lite_0
(0x40460000-0x4046ffff) axi_uart16550_3 axi4lite_0
(0x40480000-0x4048ffff) axi_uart16550_2 axi4lite_0
(0x404a0000-0x404affff) axi_uart16550_1 axi4lite_0
(0x404c0000-0x404cffff) axi_uart16550_0 axi4lite_0
(0x40600000-0x4060ffff)
UART axi4lite_0->axi2axi_connector_1->axi_interconnect_1
(0x40a00000-0x40a0ffff)
axi_spi_5 axi4lite_0->axi2axi_connector_1->axi_interconnect_1
(0x40a20000-0x40a2ffff)
axi_spi_4 axi4lite_0->axi2axi_connector_1->axi_interconnect_1
(0x40a40000-0x40a4ffff)
axi_spi_3 axi4lite_0->axi2axi_connector_1->axi_interconnect_1
(0x40a60000-0x40a6ffff)
axi_spi_2 axi4lite_0->axi2axi_connector_1->axi_interconnect_1
(0x40a80000-0x40a8ffff)
axi_spi_1 axi4lite_0->axi2axi_connector_1->axi_interconnect_1
(0x40aa0000-0x40aaffff) axi_spi_0 axi4lite_0
(0x41200000-0x4120ffff) microblaze_0_intc axi4lite_0
(0x41400000-0x4140ffff) debug_module axi4lite_0
(0x41c00000-0x41c0ffff)
axi_timer_1 axi4lite_0->axi2axi_connector_1->axi_interconnect_1
(0x41c20000-0x41c2ffff) axi_timer_0 axi4lite_0
(0x41e00000-0x41e0ffff) Ethernet_dma axi4lite_0
(0x43e00000-0x43e0ffff)
axi_epc_0 axi4lite_0->axi2axi_connector_1->axi_interconnect_1
(0x75e00000-0x75e0ffff) transmit_cntrl_0 axi4lite_0
(0x75e40000-0x75e7ffff) Ethernet axi4lite_0
(0x77a00000-0x77a0ffff)
sirene_0 axi4lite_0->axi2axi_connector_1->axi_interconnect_1
(0x7e200000-0x7e20ffff) axi_cdma_0 axi4lite_0
(0xc8000000-0xcfffffff) MCB1_DDR3 axi4_0
(0xd0000000-0xd7ffffff) MCB3_DDR3 axi4_0
INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding
PARAMETER C_LMB_NUM_SLAVES value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data
\lmb_v10_v2_1_0.mpd line 82
INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding
PARAMETER C_LMB_NUM_SLAVES value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data
\lmb_v10_v2_1_0.mpd line 82
INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block - tool is
overriding PARAMETER C_MEMSIZE value to 0x10000 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d
ata\bram_block_v2_1_0.mpd line 78
Checking platform address map ...
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi4_0 - 6 master(s) : 3 slave(s)
IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 16 slave(s)
IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s)
IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s)
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 13
slave(s)
Checking port drivers...
WARNING:EDK:4180 - PORT: s_axis_s2mm_tuser, CONNECTOR: Soft_TEMAC_dma_rxd_TUSER
- No driver found. Port will be driven to GND -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_dma_v6_03_a\data
\axi_dma_v2_1_0.mpd line 259
WARNING:EDK:4180 - PORT: s_axis_s2mm_tid, CONNECTOR: Soft_TEMAC_dma_rxd_TID - No
driver found. Port will be driven to GND -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_dma_v6_03_a\data
\axi_dma_v2_1_0.mpd line 260
WARNING:EDK:4180 - PORT: s_axis_s2mm_tdest, CONNECTOR: Soft_TEMAC_dma_rxd_TDEST
- No driver found. Port will be driven to GND -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_dma_v6_03_a\data
\axi_dma_v2_1_0.mpd line 261
WARNING:EDK:4180 - PORT: Interrupt_address_in, CONNECTOR: Interrupt_address_in -
No driver found. Port will be driven to GND -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 131
WARNING:EDK:4181 - PORT: m_axis_mm2s_tuser, CONNECTOR: Soft_TEMAC_dma_txd_TUSER
- floating connection -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_dma_v6_03_a\data
\axi_dma_v2_1_0.mpd line 227
WARNING:EDK:4181 - PORT: m_axis_mm2s_tid, CONNECTOR: Soft_TEMAC_dma_txd_TID -
floating connection -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_dma_v6_03_a\data
\axi_dma_v2_1_0.mpd line 228
WARNING:EDK:4181 - PORT: m_axis_mm2s_tdest, CONNECTOR: Soft_TEMAC_dma_txd_TDEST
- floating connection -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_dma_v6_03_a\data
\axi_dma_v2_1_0.mpd line 229
WARNING:EDK:4181 - PORT: Processor_ack_out, CONNECTOR: Processor_ack_out -
floating connection -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 132
WARNING:EDK:4181 - PORT: M_AXI_AWREGION, CONNECTOR:
axi_interconnect_1_S_AWREGION - floating connection -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi2axi_connector_v1
_00_a\data\axi2axi_connector_v2_1_0.mpd line 198
WARNING:EDK:4181 - PORT: M_AXI_ARREGION, CONNECTOR:
axi_interconnect_1_S_ARREGION - floating connection -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi2axi_connector_v1
_00_a\data\axi2axi_connector_v2_1_0.mpd line 223
Performing Clock DRCs...
INFO:EDK - Design contains multiple instances of clock_generator IP, all clock
connections should be done by user. XPS Clocking Wizard supports only one
instance of clock_generator.
INFO:EDK:4060 - INSTANCE: axi_epc_0, PARAMETER: C_PRH_CLK_PERIOD_PS - Did not
implement clock DRCs for the parameter. Top-level frequency could not be
propagated to this IP. Please make sure that you have specified the frequency
of the top-level clock port, and that the clocks are properly connected.
Performing Reset DRCs...
Overriding system level properties...
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4_0.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4_0 - tcl is overriding
PARAMETER C_RANGE_CHECK value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_
06_a\data\axi_interconnect_v2_1_0.mpd line 149
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is
overriding PARAMETER C_RANGE_CHECK value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_
06_a\data\axi_interconnect_v2_1_0.mpd line 149
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_INTERCONNECT_M_AXI_IC_READ_ISSUING value to 8 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 362
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_D_AXI value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 232
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_ADDR_TAG_BITS value to 14 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 337
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_DCACHE_ADDR_TAG value to 14 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 367
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_USE_INTERRUPT value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 401
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_USE_EXT_BRK value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 402
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_USE_EXT_NM_BRK value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 403
INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_i_bram_ctrl -
tcl is overriding PARAMETER C_MASK value to 0x40000000 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3
_10_c\data\lmb_bram_if_cntlr_v2_1_0.mpd line 92
INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_d_bram_ctrl -
tcl is overriding PARAMETER C_MASK value to 0x40000000 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3
_10_c\data\lmb_bram_if_cntlr_v2_1_0.mpd line 92
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB3_DDR3 - tcl is overriding
PARAMETER C_MEMCLK_PERIOD value to 3200 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 121
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB3_DDR3 - tcl is overriding
PARAMETER C_S0_AXI_STRICT_COHERENCY value to 0 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 164
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB3_DDR3 - tcl is overriding
PARAMETER C_S1_AXI_REG_EN0 value to 0x0000F -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 176
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB3_DDR3 - tcl is overriding
PARAMETER C_S2_AXI_REG_EN0 value to 0x0000F -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 190
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB3_DDR3 - tcl is overriding
PARAMETER C_S3_AXI_REG_EN0 value to 0x0000F -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 204
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB3_DDR3 - tcl is overriding
PARAMETER C_S4_AXI_REG_EN0 value to 0x0000F -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 218
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB3_DDR3 - tcl is overriding
PARAMETER C_S5_AXI_REG_EN0 value to 0x0000F -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 232
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB1_DDR3 - tcl is overriding
PARAMETER C_MEMCLK_PERIOD value to 3200 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 121
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB1_DDR3 - tcl is overriding
PARAMETER C_S1_AXI_REG_EN0 value to 0x0000F -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 176
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB1_DDR3 - tcl is overriding
PARAMETER C_S2_AXI_REG_EN0 value to 0x0000F -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 190
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB1_DDR3 - tcl is overriding
PARAMETER C_S3_AXI_REG_EN0 value to 0x0000F -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 204
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB1_DDR3 - tcl is overriding
PARAMETER C_S4_AXI_REG_EN0 value to 0x0000F -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 218
INFO:EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:MCB1_DDR3 - tcl is overriding
PARAMETER C_S5_AXI_REG_EN0 value to 0x0000F -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_06_a\
data\axi_s6_ddrx_v2_1_0.mpd line 232
INFO:EDK:4130 - IPNAME: axi_intc, INSTANCE:microblaze_0_intc - tcl is overriding
PARAMETER C_KIND_OF_INTR value to 0b11111111000000000000000000000000 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 87
INFO:EDK:4130 - IPNAME: axi_intc, INSTANCE:microblaze_0_intc - tcl is overriding
PARAMETER C_KIND_OF_EDGE value to 0b11111111111111111111111111111111 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 88
INFO:EDK:4130 - IPNAME: axi_intc, INSTANCE:microblaze_0_intc - tcl is overriding
PARAMETER C_KIND_OF_LVL value to 0b11111111111111111111111111111111 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 89
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_RANGE_CHECK value to 1 -
E:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_
06_a\data\axi_interconnect_v2_1_0.mpd line 149
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Invoking MIG ...
MIG returned 0
Invoking MIG ...
MIG returned 0
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
WARNING:EDK - ****************************************************************
WARNING:EDK - Optimization Alert: axi_interconnect axi4_0: One or more SI or
WARNING:EDK - MI slots uses register slices configured as "Fully-registered"
WARNING:EDK - on their AW, AR or B channels (C_S/M_AXI_AW/AR/B_REGISTER = 1).
WARNING:EDK - These control channels generally cannot take advantage of
WARNING:EDK - fully-registered performance. To reduce resources, use
WARNING:EDK - "Light-weight" reg-slices on AW, AR or B channels
WARNING:EDK - (C_S/M_AXI_AW/AR/B_REGISTER = 7).
WARNING:EDK - ****************************************************************
WARNING:EDK - Optimization Alert: axi_interconnect axi4lite_0: Port
WARNING:EDK - INTERCONNECT_ACLK is connected to a clock source slower than (or
WARNING:EDK - asynchronous to) the fastest MI slot (connected slave).
WARNING:EDK - Throughput may often be improved by connecting INTERCONNECT_ACLK
WARNING:EDK - to the same clock source as the fastest performance-critical MI
WARNING:EDK - slot.
WARNING:EDK - ****************************************************************
WARNING:EDK - Optimization Alert: axi_interconnect axi4lite_0: One or more SI
WARNING:EDK - or MI slots uses AXI4-Lite protocol and has a W or R channel
WARNING:EDK - register slice configured as "Fully-registered"
WARNING:EDK - (C_S/M_AXI_W/R_REGISTER = 1). AXI4-Lite data transfers generally
WARNING:EDK - cannot take advantage of fully-registered performance. To reduce
WARNING:EDK - resources, use "Light-weight" reg-slices on all channels of
WARNING:EDK - AXI4-Lite slots (C_S/M_AXI_*_REGISTER = 7).
WARNING:EDK - ****************************************************************
WARNING:EDK - Optimization Alert: axi_interconnect axi4lite_0: One or more SI
WARNING:EDK - or MI slots uses register slices configured as
WARNING:EDK - "Fully-registered" on their AW, AR or B channels
WARNING:EDK - (C_S/M_AXI_AW/AR/B_REGISTER = 1). These control channels
WARNING:EDK - generally cannot take advantage of fully-registered performance.
WARNING:EDK - To reduce resources, use "Light-weight" reg-slices on AW, AR or
WARNING:EDK - B channels (C_S/M_AXI_AW/AR/B_REGISTER = 7).
WARNING:EDK - ****************************************************************
WARNING:EDK - ** MicroBlaze - microblaze_0
WARNING:EDK - ****************************************************************
WARNING:EDK - ** ICACHE address space [0xC0000000:0xDFFFFFFF] contains an area
WARNING:EDK - ** without assigned addresses [0xC0000000:0xC3FFFFFF] on bus
WARNING:EDK - ** "axi4_0".
WARNING:EDK - ****************************************************************
WARNING:EDK - ****************************************************************
WARNING:EDK - ** MicroBlaze - microblaze_0
WARNING:EDK - ****************************************************************
WARNING:EDK - ** ICACHE address space [0xC0000000:0xDFFFFFFF] contains an area
WARNING:EDK - ** without assigned addresses [0xD8000000:0xDFFFFFFF] on bus
WARNING:EDK - ** "axi4_0".
WARNING:EDK - ****************************************************************
WARNING:EDK - ****************************************************************
WARNING:EDK - ** MicroBlaze - microblaze_0
WARNING:EDK - ****************************************************************
WARNING:EDK - ** ICACHE address space [0xC0000000:0xDFFFFFFF] contains an area
WARNING:EDK - ** without assigned addresses [0xC4080000:0xC7FFFFFF] on bus
WARNING:EDK - ** "axi4_0".
WARNING:EDK - ****************************************************************
WARNING:EDK - ****************************************************************
WARNING:EDK - ** MicroBlaze - microblaze_0
WARNING:EDK - ****************************************************************
WARNING:EDK - ** DCACHE address space [0xC0000000:0xDFFFFFFF] contains an area
WARNING:EDK - ** without assigned addresses [0xC0000000:0xC3FFFFFF] on bus
WARNING:EDK - ** "axi4_0".
WARNING:EDK - ****************************************************************
WARNING:EDK - ****************************************************************
WARNING:EDK - ** MicroBlaze - microblaze_0
WARNING:EDK - ****************************************************************
WARNING:EDK - ** DCACHE address space [0xC0000000:0xDFFFFFFF] contains an area
WARNING:EDK - ** without assigned addresses [0xD8000000:0xDFFFFFFF] on bus
WARNING:EDK - ** "axi4_0".
WARNING:EDK - ****************************************************************
WARNING:EDK - ****************************************************************
WARNING:EDK - ** MicroBlaze - microblaze_0
WARNING:EDK - ****************************************************************
WARNING:EDK - ** DCACHE address space [0xC0000000:0xDFFFFFFF] contains an area
WARNING:EDK - ** without assigned addresses [0xC4080000:0xC7FFFFFF] on bus
WARNING:EDK - ** "axi4_0".
WARNING:EDK - ****************************************************************
INTC INFO:: Processor_clk not connected.. IRQ to Microblaze is generated on AXI
clock.
INFO:coreutil - Full license for component <axi_ethernet_soft_tri_mode> allows
you to use this component. This license does not give you access to source
code implementing this component.
The license for this core was generated for XXXXX.YYYY@ZZZZZ.com on
07/17/2013It is the responsibility of the Licensee of this core to adhere to
all terms and conditions of the applicable license agreement when using this
core.
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
INFO: No asynchronous clock conversions in axi_interconnect axi4_0.
INFO: No asynchronous clock conversions in axi_interconnect axi4lite_0.
INFO: Setting timing constaints for microblaze_0.
INFO: The microblaze_0 core has constraints automatically generated by XPS in
implementation/microblaze_0_wrapper/microblaze_0_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: Setting timing constaints for microblaze_0_ilmb.
INFO: The microblaze_0_ilmb core has constraints automatically generated by XPS
in implementation/microblaze_0_ilmb_wrapper/microblaze_0_ilmb_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: Setting timing constaints for microblaze_0_dlmb.
INFO: The microblaze_0_dlmb core has constraints automatically generated by XPS
in implementation/microblaze_0_dlmb_wrapper/microblaze_0_dlmb_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: Forcing parameter C_SIMULATION = "FALSE" in IP axi_s6_ddrx.
INFO: Forcing parameter C_SIMULATION = "FALSE" in IP axi_s6_ddrx.
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.
Modify defaults ...
Creating stub ...
Processing licensed instances ...
IPNAME:axi_ethernet INSTANCE:Ethernet -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 415 - processing license
WARNING:coreutil:8 - Feature <axi_ethernet_avb@2012.04> is enabled with a
Hardware_Evaluation license.
WARNING:coreutil:8 - Feature <axi_ethernet_avb@2012.04> is enabled with a
Hardware_Evaluation license.
Completion time: 29.00 seconds
Creating hardware output directories ...
Managing hardware (BBD-specified) netlist files ...
IPNAME:transmitter INSTANCE:transmitter_0 -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 897 - Copying
(BBD-specified) netlist files.
Managing cache ...
Elaborating instances ...
IPNAME:bram_block INSTANCE:microblaze_0_bram_block -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 231 - elaborating IP
IPNAME:clock_generator INSTANCE:clock_generator_0 -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 251 - elaborating IP
ClkGen elaborate status: PASSED
----------------------------------------
----------------------------------------
IPNAME:clock_generator INSTANCE:clock_generator_1 -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 271 - elaborating IP
ClkGen elaborate status: PASSED
----------------------------------------
----------------------------------------
Writing HDL for elaborated instances ...
Inserting wrapper level ...
Completion time: 1.00 seconds
Constructing platform-level connectivity ...
WARNING:EDK:4059 - INSTANCE: Ethernet, Overriding connection of PORT:
AXI_STR_TXD_ARESETN, VALUE: AXI_STR_TXD_ARESETN - which is part of the
connected BUSIF: S_AXI - E:\projects\DoLOG_146\FPGATransmitter\system.mhs
line 415
WARNING:EDK:4059 - INSTANCE: Ethernet, Overriding connection of PORT:
AXI_STR_TXC_ARESETN, VALUE: AXI_STR_TXC_ARESETN - which is part of the
connected BUSIF: S_AXI - E:\projects\DoLOG_146\FPGATransmitter\system.mhs
line 415
WARNING:EDK:4059 - INSTANCE: Ethernet, Overriding connection of PORT:
AXI_STR_RXD_ARESETN, VALUE: AXI_STR_RXD_ARESETN - which is part of the
connected BUSIF: S_AXI - E:\projects\DoLOG_146\FPGATransmitter\system.mhs
line 415
WARNING:EDK:4059 - INSTANCE: Ethernet, Overriding connection of PORT:
AXI_STR_RXS_ARESETN, VALUE: AXI_STR_RXS_ARESETN - which is part of the
connected BUSIF: S_AXI - E:\projects\DoLOG_146\FPGATransmitter\system.mhs
line 415
Completion time: 0.00 seconds
Writing (top-level) BMM ...
Writing (top-level and wrappers) HDL ...
Generating synthesis project file ...
Running XST synthesis ...
INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INSTANCE:axi4_0 - E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 132 -
Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:axi4lite_0 - E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 139
- Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0 - E:\projects\DoLOG_146\FPGATransmitter\system.mhs line
147 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_ilmb - E:\projects\DoLOG_146\FPGATransmitter\system.mhs
line 199 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_dlmb - E:\projects\DoLOG_146\FPGATransmitter\system.mhs
line 206 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_i_bram_ctrl -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 213 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_d_bram_ctrl -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 222 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_bram_block -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 231 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:proc_sys_reset_0 - E:\projects\DoLOG_146\FPGATransmitter\system.mhs
line 238 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:clock_generator_0 - E:\projects\DoLOG_146\FPGATransmitter\system.mhs
line 251 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:clock_generator_1 - E:\projects\DoLOG_146\FPGATransmitter\system.mhs
line 271 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:debug_module - E:\projects\DoLOG_146\FPGATransmitter\system.mhs line
293 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:uart - E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 306 -
Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:mcb3_ddr3 - E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 321 -
Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:mcb1_ddr3 - E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 370 -
Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:ethernet - E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 415 -
Running XST synthesis
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
ERROR:EDK:546 - Aborting XST flow execution!
INFO:EDK:2246 - Refer to
E:\projects\DoLOG_146\FPGATransmitter\synthesis\system_ethernet_wrapper_xst.s
rp for details
Running NGCBUILD ...
IPNAME:system_axi4_0_wrapper INSTANCE:axi4_0 -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 132 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: E:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx150fgg484-3 -intstyle silent -i -sd .. system_axi4_0_wrapper.ngc
../system_axi4_0_wrapper
Reading NGO file
"E:/projects/DoLOG_146/FPGATransmitter/implementation/axi4_0_wrapper/system_axi4
_0_wrapper.ngc" ...
Loading design module "../system_axi4_0_wrapper_fifo_generator_v9_1_1.ngc"...
Loading design module "../system_axi4_0_wrapper_fifo_generator_v9_1_2.ngc"...
Loading design module "../system_axi4_0_wrapper_fifo_generator_v9_1_3.ngc"...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_axi4_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 3 sec
Total CPU time to NGCBUILD completion: 3 sec
Writing NGCBUILD log file "../system_axi4_0_wrapper.blc"...
NGCBUILD done.
IPNAME:system_axi4lite_0_wrapper INSTANCE:axi4lite_0 -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 139 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: E:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx150fgg484-3 -intstyle silent -i -sd .. system_axi4lite_0_wrapper.ngc
../system_axi4lite_0_wrapper
Reading NGO file
"E:/projects/DoLOG_146/FPGATransmitter/implementation/axi4lite_0_wrapper/system_
axi4lite_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_axi4lite_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../system_axi4lite_0_wrapper.blc"...
NGCBUILD done.
IPNAME:system_microblaze_0_wrapper INSTANCE:microblaze_0 -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 147 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: E:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx150fgg484-3 -intstyle silent -i -sd .. system_microblaze_0_wrapper.ngc
../system_microblaze_0_wrapper
Reading NGO file
"E:/projects/DoLOG_146/FPGATransmitter/implementation/microblaze_0_wrapper/syste
m_microblaze_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_microblaze_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 3 sec
Total CPU time to NGCBUILD completion: 3 sec
Writing NGCBUILD log file "../system_microblaze_0_wrapper.blc"...
NGCBUILD done.
IPNAME:system_microblaze_0_ilmb_wrapper INSTANCE:microblaze_0_ilmb -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 199 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: E:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx150fgg484-3 -intstyle silent -i -sd ..
system_microblaze_0_ilmb_wrapper.ngc ../system_microblaze_0_ilmb_wrapper
Reading NGO file
"E:/projects/DoLOG_146/FPGATransmitter/implementation/microblaze_0_ilmb_wrapper/
system_microblaze_0_ilmb_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_microblaze_0_ilmb_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../system_microblaze_0_ilmb_wrapper.blc"...
NGCBUILD done.
IPNAME:system_microblaze_0_dlmb_wrapper INSTANCE:microblaze_0_dlmb -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 206 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: E:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx150fgg484-3 -intstyle silent -i -sd ..
system_microblaze_0_dlmb_wrapper.ngc ../system_microblaze_0_dlmb_wrapper
Reading NGO file
"E:/projects/DoLOG_146/FPGATransmitter/implementation/microblaze_0_dlmb_wrapper/
system_microblaze_0_dlmb_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_microblaze_0_dlmb_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../system_microblaze_0_dlmb_wrapper.blc"...
NGCBUILD done.
IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 251 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: E:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx150fgg484-3 -intstyle silent -i -sd ..
system_clock_generator_0_wrapper.ngc ../system_clock_generator_0_wrapper
Reading NGO file
"E:/projects/DoLOG_146/FPGATransmitter/implementation/clock_generator_0_wrapper/
system_clock_generator_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...
NGCBUILD done.
IPNAME:system_clock_generator_1_wrapper INSTANCE:clock_generator_1 -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 271 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: E:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx150fgg484-3 -intstyle silent -i -sd ..
system_clock_generator_1_wrapper.ngc ../system_clock_generator_1_wrapper
Reading NGO file
"E:/projects/DoLOG_146/FPGATransmitter/implementation/clock_generator_1_wrapper/
system_clock_generator_1_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_clock_generator_1_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../system_clock_generator_1_wrapper.blc"...
NGCBUILD done.
IPNAME:system_mcb3_ddr3_wrapper INSTANCE:mcb3_ddr3 -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 321 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: E:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx150fgg484-3 -intstyle silent -i -sd .. system_mcb3_ddr3_wrapper.ngc
../system_mcb3_ddr3_wrapper
Reading NGO file
"E:/projects/DoLOG_146/FPGATransmitter/implementation/mcb3_ddr3_wrapper/system_m
cb3_ddr3_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_mcb3_ddr3_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../system_mcb3_ddr3_wrapper.blc"...
NGCBUILD done.
IPNAME:system_mcb1_ddr3_wrapper INSTANCE:mcb1_ddr3 -
E:\projects\DoLOG_146\FPGATransmitter\system.mhs line 370 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<E:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: E:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx150fgg484-3 -intstyle silent -i -sd .. system_mcb1_ddr3_wrapper.ngc
../system_mcb1_ddr3_wrapper
Reading NGO file
"E:/projects/DoLOG_146/FPGATransmitter/implementation/mcb1_ddr3_wrapper/system_m
cb1_ddr3_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_mcb1_ddr3_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../system_mcb1_ddr3_wrapper.blc"...
NGCBUILD done.
INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.
If any constraint needs to be overridden, this should be done by modifying
the data/system.ucf file.
Rebuilding cache ...
ERROR:EDK:440 - platgen failed with errors!
Done!