I am working through the Quartus Prime Introduction Using Schematic Diagrams tutorial for Quartus Prime Lite 16. (I am using version 16.0.2 on Windows.) Because I have a DE1-SoC board, I specified that board and the corresponding device when creating the project:
My circuit includes inputs named x1 and x2 and an output named f. In the assignment editor, I renamed SW[0] and SW[1] and the output pins LEDR[0], respectively, to my signal names. I ended up with:
The pin assignments are shown in my circuit diagram:
However, the assignments don't seem to be working correctly. I get these messages when I compile:
Warning (15714): Some pins have incomplete I/O assignments. Refer to
the I/O Assignment Warnings report for details
Critical Warning
(169085): No exact pin location assignment(s) for 3 pins of 241 total
pins. For the list of pins please refer to the I/O Assignment Warnings
table in the fitter report.
The fitter report includes:
210 LEDR[0] Missing location assignment
211 SW[0] Missing location assignment
212 SW[1] Missing location assignment
How do I assign signal names to pins correctly?
UPDATE
Here is the list of files for the project:
DE1_SOC_golden_top.sdc [which I did not manually create]
light.bdf
Waveform.vwf
When I double-click on DE1_SOC_golden_top.sdc, I get an error:
Can't open file DE1_SOC_golden_top.sdc -- file does not exist
I also see these messages when I compile:
Info (12021): Found 1 design units, including 1 entities, in source file light.bdf
Info (12023): Found entity 1: light
Warning (12125): Using design file de1_soc_golden_top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: DE1_SOC_golden_top
Info (12127): Elaborating entity "DE1_SOC_golden_top" for the top level hierarchy