This article describes using an industrial-grade field-programmable gate array (FPGA) as a coprocessor or system on a chip (SoC) to bring flexibility to industrial applications. Providing a single, highly integrated platform for multiple industrial products, FPGAs can substantially reduce development time and risk.
The full article is available here.
Programmable logic devices (PLDs) are a critical component in embedded industrial designs. PLDs have evolved in industrial designs from providing simple glue logic, to the use of an FPGA as a coprocessor. This technique allows for I/O expansion and off loads the primary microcontroller (MCU) or digital signal processor (DSP) device in applications such as communications, motor control, I/O modules, and image processing.
As system complexity increases, FPGAs also offer the ability to integrate an entire SoC, at a lower cost compared to discrete MCU, DSP, ASSP, or ASIC solutions.
Whether used as a coprocessor or SoC, Altera FPGAs offer the following advantages for your industrial applications:
Design integration: simplify and reduce cost by using an FPGA as a coprocessor or SoC that integrates the IP and software stacks on a single device platform.
Reprogrammability: adapt industrial designs to evolving protocols, IP improvements, and new hardware features within one FPGA on a common development platform.
Performance scaling: enhance performance via embedded processors, custom instructions, and IP blocks within the FPGA to meet your system requirements.
Obsolescence protection: increase industrial product life cycles and provide protection against hardware obsolescence through long FPGA life cycles and device migration to new FPGA families.
Familiar tools: use familiar, powerful, and integrated tools to simplify design and software development, IP integration, and debugging.
The following sections discuss these advantages in greater detail.
Designers of modern industrial systems face many challenges, including system complexity, changing standards, performance requirements, and total system cost, as illustrated in Fig. 1.
Fig. 1: Key industrial design challenges.
As a designer of industrial systems, you can determine whether to use an FPGA as a coprocessor (also referred to as an I/O companion or I/O hub device) or as a complete SoC solution. You can combine standard host processors with FPGAs on the same board, with the external host processor performing system processing.
However, fixed function processors frequently lack the key interfaces, functionality, or performance for industrial applications. You can offload the processor by moving some of the processing tasks inside the FPGA. Alternatively, you can integrate all processor functions on a single FPGA-based SoC platform to simplify design complexity and reduce overall system cost.
Many MCU or DSP solutions exceed bandwidth if required to run both motor control tasks and communications concurrently. As a result, you may be required to add another ASSP, MCU, or FPGA device, often as an expensive add-on card, if your current board cannot accommodate this extra device. Similarly, different fieldbus and evolving industrial Ethernet protocol standards may require a specific ASSP, MCU, or FPGA device for each protocol. This may be required because some standards require protocol-specific hardware (MAC) and a protocol-specific software stack. FPGAs allow you to integrate system functions in the coprocessor and to change your design as needed at any time
Fig. 2 illustrates a motion or motor control platform that takes advantage of Altera FPGAs as coprocessors for both the DSP offload engine and industrial networking. A motor controller sets the energy efficiency and accuracy of an electric motor through the control of speed and electrical current (translated into a torque setting). Similarly, motion control focuses on the precision of position and timing. In many cases, the electronic hardware is similar, and the control software, or algorithms, and I/O interfaces are the differentiating factors.The example in Fig. 2 shows a typical controller that depends on a primary MCU or DSP device (host processor) to run the algorithm, driving the power stage of a motor or motion controller. When the host processor reaches its performance limit, designers can increase the device clock speed to boost processor performance. However, there is a limit to the performance gains, and this method may also introduce other problems, such as the need to upgrade to faster memory, the performance of other hardware, and additional time required to optimise software.
In such cases, offloading some of the host processor functions to the FPGA coprocessor can provide relief, and using an FPGA for the communications provides you the flexibility to change with evolving standards like Industrial Ethernet protocols. You can then reprogram the FPGA and use the same hardware platform to meet your needs.
Fig. 2: FPGA as motion/motor control coprocessor.
Integrating design components on a single SoC FPGA device platform further simplifies design complexity and reduces overall system cost. Fig. 3 illustrates a simple industrial motor control system in which the FPGA now functions as the SoC, integrating DSP blocks, memory, video graphics controllers, motor encoders, and other components. You can simply add PHYs and other analog and power components to complete the design.
Fig. 3: FPGA as SoC motion/motor control.
In addition, motor control applications often require a feedback mechanism to calculate current speed and position. Many optimised digital encoder interface IP cores are available only as IP for FPGAs, supporting the use of an FPGA for the interface. IP integration on the FPGA reduces board size, component count, assembly complexity, and stocking requirements. This integration increases system reliability with fewer components on the board. Altera FPGAs support many other system functions such as embedded processors, DSP blocks, LCD displays, and video processors.
Fig. 4 illustrates another application example with the FPGA acting as a coprocessor in a video surveillance application. The video surveillance market is increasingly adopting wide dynamic range (WDR) camera sensors capable of distinguishing target objects from the background through adverse lighting conditions. Only FPGAs have the bandwidth to act as the coprocessor for the WDR image sensor pipeline (ISP), feeding the video stream to the DSP device for video encoding, such as H.264. A DSP device lacks the bandwidth and interfaces to handle WDR ISP, and lacks the performance to run additional surveillance functions, such as video analytics.
Fig. 4: FPGA as coprocessor – WDR IP surveillance camera.
Alternatively, Fig. 5 shows the FPGA as SoC in the video surveillance application. When used as a SoC, FPGAs enable you to integrate all components – ISP, video analytics, encoding, and networking – in a single FPGA device. This technique eliminates the need for a back-end DSP device, and provides a more compact and integrated design.
Fig. 5: FPGA as SoC – WDR IP surveillance camera.
Fig. 6 shows the block diagram for the example system implemented on the Cyclone V SoC.
Fig. 6: SoC block diagram – DR IP surveillance camera.
Reprogrammability
FPGA reprogrammability enables you to adapt to changing standards and support design reuse. Even if you target a single MCU, DSP, ASSP, or ASIC solution for your industrial application, many applications still require a separate device, such as an optional fieldbus-specific ASIC or FPGA, to handle features like industrial communications, as shown in Fig. 7. When networking specifications or feature requirements change, you are often forced to create multiple PCBs to support different protocols and features, requiring additional software porting cycles on each platform. This can significantly increase the total solution cost.
Fig. 7: Fieldbus migration to industrial Ethernet.
Alternatively, you can use an FPGA as the communication coprocessor. You can design one communications subsystem, change the networking protocol at any time, and support multiple products on a single hardware platform. You can gain even more flexibility by integrating the main MCU or DSP control functions, multiple processors, and other IP and interfaces into a single FPGA design to create a smaller device footprint and save on space and cost.
With the ability to leverage one platform for multiple products, you can realis significant time to market advantages of several months or more because you have less hardware to develop and your software porting matrix is simplified.
Performance scaling
A key part of any industrial control system is the processing functions of a host/primary MCU, DSP, ASIC, or ASSP device. When performance is the design challenge, FPGAs provide the following ways to scale the processing performance, as illustrated in Fig. 8.
Use either a high-performance external processor along with one to multiple embedded processors inside the FPGA. You can also integrate all processing functions into the FPGA as the SoC.
Add custom instructions in line with your processor code to accelerate specific processor instructions; floating point is a great example.
Accelerate data transformation with application-specific hardware, like DSP blocks.
Fig. 8: FPGA performance scaling methods.
Multicore processing
For flexible multiprocessor designs, you can choose from several implementations. Embedded industrial designers are commonly interested in asymmetrical coprocessing, with the FPGA as either the I/O companion chip or SoC. Asymmetric multiprocessing means that multifunction products can have a dedicated processor for each main function. This is especially suited to today’s demanding applications, such as smart phones. Developers formerly built systems such as this with multiple processors on the PCB. Now you can accomplish this with dedicated processing blocks partitioned within a single FPGA, as shown in Fig. 9.
Fig. 9: FPGA as SoC asymmetric multicore and as coprocessor.
An example of this type of application is a high-performance servo drive that requires a primary, high-performance processor (or multiple processors) to perform each main function. A dedicated processor executes the application code, a communications processor provides the fieldbus or Ethernet link, a graphics or image processor provides the display, and includes other custom logic and interfaces like digital motor encoders, PWM functions, and power control. You can integrate all of these functions into the FPGA either as a coprocessor or complete SoC.
Custom istructions
You can accelerate time-critical software algorithms by adding custom instructions to the embedded processor instruction set. The example in Fig. 10 shows how you can add custom instruction logic to the arithmetic logic unit (ALU) of Altera’s Nios II processor. Using custom instructions reduces a complex sequence of standard instructions to a single in-line instruction implemented in hardware. You can use this feature for a variety of applications. For example, you can optimize software inner loops for DSP, packet header processing, and computation-intensive applications. The Quartus II software provides a configuration GUI that supports up to 256 custom instructions to the Nios II processor. The example in Fig. 10 uses a 64 Kilobyte (KB) CRC buffer. The custom instruction can accelerate CPU performance by up to 27 times faster than software-only operation in a Nios II processor.
The Nios II processor single-precision, floating-point custom instructions are another good example of accelerating processor operations. These instructions accelerate FPGA performance significantly for division, multiplication, subtraction, and addition functions. Other processor architectures operate on similar principles. The actual performance acceleration of custom instructions may vary by processor and custom instruction.
Hardware aceleration
In addition to custom instructions, you can use hardware accelerators, such as DSP blocks, video blocks, and other IP, to clear data bottlenecks. Fig. 11 illustrates the use of concurrent, or parallel, data coprocessing to increase system performance by up to 530 times faster than the same Nios II processor system running only custom instructions. During concurrent data coprocessing, the central processing unit (CPU) of the processor starts and stops the coprocessor, the coprocessor fetches data and stores results, and the CPU runs application code concurrently. This is ideal for block data operations, such as DSP functions often used in motor or motion control applications.
Obsolescence protection
Most MCU, DSP, or ASSP devices have significantly shorter life cycles than FPGAs because their vendors typically obsolete mature devices sooner than Altera. These types of devices are designed to fulfil specific applications for high-volume customers over a shorter period of time. In addition, although current ASIC devices in production may have a life cycle of 15 years or more, many are nearing their end-of- life, forcing designers to consider other long-term options such as FPGAs. Although new ASIC designs are in development, designers often cannot change these products fast enough to keep pace with evolving standards or new features required over time.
Conversely, FPGAs serve a wide range of applications and markets and are independent of any particular application for volume production. Therefore, it is cost effective for Altera to manufacture FPGAs over a longer period. You can better manage the stability of the supply chain, which may include many other semiconductor components. While using an FPGA platform for your design, you can update and change your designs, at any time. You can also reuse IP and port designs to newer FPGA families in a much less time than it takes to design a new MCU, DSP, ASSP, or ASIC.
Over time, Altera FPGAs help you improve the commercial viability of multiple product lines, while helping you contain the cost of product obsolescence
Conclusion
Altera FPGAs provide the flexibility to adapt industrial designs to changing requirements and lower total solution costs. With a single FPGA, you can easily integrate part of your design into a single device, and then re-program your FPGA- based design, at any time – in both local and remote locations. This approach maximises your design’s ability to change with evolving standards, while minimising the number of board designs required to support each protocol standard or each additional feature.
Altera FPGAs are ideal for parallel signal processing and therefore ideal for any system requiring a performance boost via hardware acceleration. Parallel hardware in the FPGA means no performance cost to add more controllers and features. You can accelerate performance with embedded processors and IP blocks on an FPGA used as either a coprocessor or SoC in your design.
Your software team can also capitalise on standard OS and BSP, and application software expertise and port applications to run on one FPGA platform instead of across multiple MCU or DSP devices. C code is portable across processor architectures.
One FPGA platform can support multiple product lines and provide a commercially meaningful, fast, and cost-efficient way to deploy solutions to market. The integration and flexibility benefits of FPGAs, such as the MAX 10 or Cyclone family of FPGA devices, enable you to deliver products to market faster than with other technologies, thus maximising market share, and extending the life cycle of your industrial designs.
The full article is available here.
Contact Saro Murabito, EBV Elektronik, Tel 011 236-1900, saro.murabito@ebv.com
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